Fujitsu MB90420/5 (A) Series Hardware Manual page 13

Fig. 1.1 Block Diagram .................................................................................................................1-6
Fig. 1.2 Package Dimension (QFP100) .......................................................................................1-7
Fig. 1.3 Package Dimension (LQFP100) .....................................................................................1-8
Fig. 1.4 Pin Assignment (QFP100) ..............................................................................................1-9
Fig. 1.5 Pin Assignment (LQFP100) ..........................................................................................1-10
Fig. 1.6 Example of using external clock .................................................................................1-17
Fig. 1.7 Power Input Pins (V
Fig. 1.8 Undefined-value Output Timing Chart ........................................................................1-18
Fig. 2.1 Example of Relationships between F2MC-16LX System and Memory Map..............2-4
Fig. 2.2 Memory Map ....................................................................................................................2-6
Fig. 2.3 Memory Management in Linear and Bank Types.........................................................2-7
Fig. 2.4 Example of 24-bit Physical Direct Addressing in Linear Types .................................2-8
Fig. 2.5 Exam ple of 32-bit Ggeneral-purpose Register Indirect Specification in Linear Type........2-8
Fig. 2.6 Example of Bank Type Addressing .............................................................................2-10
Fig. 2.7 Storage of Multi-byte Data in RAM ..............................................................................2-11
Fig. 2.8 Storage of Multi-byte Operand.....................................................................................2-11
Fig. 2.9 Storage of Multi-byte Length Data in Stack................................................................2-12
Fig. 2.10 Access to Multi-byte Length Data on Bank Boundary ..............................................2-12
Fig. 2.11 Dedicated and General-purpose Registers ................................................................2-13
Fig. 2.12 Configuration of Dedicated Registers.........................................................................2-14
Fig. 2.13 Data Transfer to Accumulator......................................................................................2-16
Fig. 2.14 Example of Transfer between AL and AH of Accumulator (A)
(8-bit immediate value, zero-extended).......................................................................2-17
Fig. 2.15 Example of Transfer between AL and AH of Accumulator (A)
(8-bit immediate value, sign-extended).......................................................................2-17
Fig. 2.16 Example of 32-bit Data Transfer to Accumulator (A) (register indirect)..................2-18
Fig. 2.17 Example of Transfer between AL and AH of Accumulator (A)
(16-bit, register indirect) ...............................................................................................2-18
Fig. 2.18 Stack Operation Instructions and Stack Pointers .....................................................2-20
Fig. 2.19 Configuration of Processor Status (PS) .....................................................................2-21
Fig. 2.20 Configuration of Condition Code Register (CCR)......................................................2-22
Fig. 2.21 Configuration of Register Bank Pointer (RP) .............................................................2-23
Fig. 2.22 Physical Address Conversion Rules in General-purpose Register Area................2-23
Fig. 2.23 Configuration of Interrupt Level Mask Register (ILM) ...............................................2-24
Fig. 2.24 Program Counter (PC) .................................................................................................. 2-25
Fig. 2.25 Generation of Physical Address in Direct Page Register (DPR) ..............................2-26
Fig. 2.26 Direct Page Register (DPR) Setting and Data Access Example...............................2-26
Fig. 2.27 Allocation and Configuration of General-Purpose Register Banks in Mem ory Space ....2-28
Fig. 2.28 Interrupt/hold Inhibition................................................................................................2-34
Fig. 2.29 Interrupt/hold Inhibition Instruction and Prefix Code ...............................................2-35
Fig. 2.30 Successive Prefix Codes..............................................................................................2-35
Figures
/V ) ...........................................................................................1-17
CC SS
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