Block Diagram Of Can Controller; Fig. 23.1 Block Diagram Of Can Controller - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

23.2 Block Diagram of CAN Controller

Figure 23.1 shows a block diagram of the CAN controller.
n Block diagram of CAN controller
2
F MC-16LX bus
Clock
PSC
PR
BTR
PH
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
NS1, 0
RTEC
BVALR
TREQR
TCANR
TRTRR
RFWTR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
AMSR
AMR0
AMR1
IDR0 to 15
DLCR0 to 15
DTR0 to 15
RAM
LEIR
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
Prescaler 1 to 64
Bit timing generation
frequency division
Node status
Node status change
change interrupt
interrupt generation
TBF , clear
X
Transmit buffer
x
TBF
decision
TBF
X
TBF , set, clear
X
Transmission complete
Transmission
interrupt generation
complete
interrupt
RBF , set
X
Reception complete
Reception
interrupt generation
complete
interrupt
RBF , TBF , set, clear
X X
, set IDSEL
RBF
X
0
1
Acceptance Receive buffer
decision
filter
RAM address
RBF , TBF
X
generation

Fig. 23.1 Block Diagram of CAN Controller

TQ (Operating clock)
SYNC, TSEG1, TSEG2
Error
control
Transmit/
receive sequencer
Data Acceptance
X
counter filter control
TDLC RDLC IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
Transmit shift
register
TDLC
CRCER
RDLC CRC generation/
error check
Receive shift
register
ARBLOST
BITER
x
ACKER
RBF
FRMER
X
, RDLC, TDLC, IDSEL
X
23-4
IDLE, SUSPND,
transmit, receive,
Bus state
ERR, OVRLD
machine
Error frame
generation
Overload
frame
generation
Output
ARBLOST
driver
Stuffing
CRC ACK
generation generation
STFER
Destuffing/stuffing
error check
Arbitration
check
Bit error
check
Acknowledgment
error check
Input
Form error
check
TX
PH1
RX
latch