Timer Mode - Fujitsu MB90420/5 (A) Series Hardware Manual

5.5.3 Timer Mode

In the timer mode, functions except the sub-clock and the watch timer stop; almost all the chip functions
stop.
n Transition to timer mode
A transition is performed to the timer mode when 0 is written to the TMD bit of the low-power consumption
mode control register (LPMCR) in the sub-clock mode (CKSCR: SCS = 0).
• Data hold function
In the timer mode, data in the dedicated registers such as an accumulator and internal RAM are stored.
• Operation during interrupts request issuance
During interrupt request issuance, writing 1 to TMD bit of the low-power consumption mode control register
(LPMCR) does not transit the mode to the timer mode.
• Pin state
The SPL bit of the low-power consumption mode control register (LPMCR) controls whether to set the
external pin to the immediately preceding state or to the high impedance state in the timer mode.
n Cancellation of timer mode
The low-power consumption controller cancels the timer mode at a reset input or a generation of interrupt.
• Return by areset
When the watch mode is cancelled by a reset factor, the timer mode is cancelled and then the oscillation
stabilization wait reset state occurs. The reset sequence is executed after the oscillation stabilization wait
time has elapsed.
• Return by an interrupt
When an interrupt request with a higher interrupt level than 7 is issued from a resource, during the timer
mode (the interrupt control register ICR:IL2, IL1 and IL0 = except for 111
controller cancels the timer mode and then immediately transitions to the sub-clock mode. After the
transition to the sub-clock mode, normal interrupt handling is performed. Interrupt handling is performed
when an interrupt is accepted by setting of the I flag of the condition code register (CCR), the interrupt level
mask register (ILM) and the interrupt control register (ICR). When the CPU is not ready to accept an
interrupt, it executes the interrupt handling from the instruction next to the one specifying.
Note: Normally, interrupt processing is performed after execution of the instruction present immediately
after the instruction that specifies the timer mode.
LOW-POWER CONSUMPTION MODE
5-15
), the low-power consumption
B