Fujitsu MB90420/5 (A) Series Hardware Manual page 22

Table 16-7 Function of Each Bit of Request Level Setting Register (ELVR) ....................... 16-10
Table 16-8 Correspondence between DTP/Interrupt Control Registers (EIRR and ENIR)
and Each Channel................................................................................................... 16-11
Table 16-9 Control Bits and Interrupt Factors for DTP/External Interrupt Circuit .............. 16-13
Table 19-1 Conversion Modes of 8-/10-bit A/D Converter ....................................................... 19-3
Table 19-2 8-/10-bit A/D Converter Interrupt and EI
Table 19-3 Pins of 8-/10-bit A/D Converter................................................................................ 19-6
Table 19-4 Function of Each Bit of A/D Control Status Register Higher (ADCSH) ............. 19-10
Table 19-5 Function of Each Bit of A/D Control Status Register Lower (ADCSL) .............. 19-12
Table 19-6 Function of Each Bit of A/D Data Register (ADCR) ............................................. 19-14
Table 19-7 Interrupt Control Bits and Interrupt Factors of 8-/10-bit A/D Converter ........... 19-15
Table 19-9 8-/10-bit A/D Converter Interrupt and EI
Table 23-1 List of Overall Control Registers ............................................................................ 23-5
Table 23-2 List of CAN WAKE UP Control Registers............................................................... 23-6
Table 23-3 List of Message Buffers (ID Registers)................................................................... 23-7
Table 23-4 List of Message Buffers (DLC Registers)............................................................... 23-9
Table 23-5 List of Message Buffers (Data Registers) ............................................................ 23-10
Table 23-6 Correspondence between NS1 and NS0 and Node Status................................. 23-13
Table 23-7 Selection of Acceptance Mask .............................................................................. 23-25
Table 24-1 Detection Voltage of Detection Reset Circuit for Low Voltage and
CPU Operation .......................................................................................................... 24-3
Table 24-2 Interval Time for CPU Operation Detection Reset Circuit .................................... 24-3
Table 24-3 Explanation of Function of Each Bit of Low Voltage and
CPU Operation Detection Reset Control Register ................................................ 24-6
Table 24-4 Operation Stabilization Wait Time .......................................................................... 24-7
Table 25-1 Flash Memorr Control Signals................................................................................. 25-7
Table 25-2 Command Sequence List....................................................................................... 25-10
Table 25-3 Bit Allocation of Hardware Sequence Flags ........................................................ 25-11
Table 25-4 List of Functions of Hardware Sequence Flags .................................................. 25-11
Table 25-5 State Transition of Data Polling Flag (State change at normal operation) ....... 25-12
Table 25-6 State Transition at Abnormal Operation (State change at abnormal operation)25-12
Table 25-7 State Transition of Toggle Bit Flag (State change at normal operation) .......... 25-13
Table 25-8 State Transition of Toggle Bit Flag (State change at abnormal operation) ...... 25-13
Table 25-9 State Transition of Timing Limit Exceeding Flag
(State change at normal operation) ...................................................................... 25-14
Table 25-10 State Transition of Timing Limit Exceeding Flag
(State change at abnormal operation) .................................................................. 25-14
Table 25-11 State Transition of Sector Erase Timer Flag
(State change at normal operation) ...................................................................... 25-15
Table 25-12 State Transition of Sector Erase Timer Flag
(State change at abnormal operation) .................................................................. 25-15
Table 26-1 Pins Used for Fujitsu Standard Serial Onboard Writing....................................... 26-3
Table 26-2 Flash Microcontroller Programmer System Configuration
(Manufactured by Yokogawa Digital Computer Ltd.)............................................ 26-4
2
OS .......................................................... 19-3
2
OS ........................................................ 19-15
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