Sound Control Register - Fujitsu MB90420/5 (A) Series Hardware Manual

20.2.1 Sound Control Register

The sound control register controls the operation status of the sound generator by controlling interrupts and
setting the external output pins.
n Sound Control Register
Sound control register (upper)
Address: 00005B
H
Read/write →
Initial value →
Sound control register (lower)
Address: 00005A
H
Read/write →
Initial value →
[bit 15] TST : Test bit
This bit is prepared for the device test. In any user applications, it should be set to "0".
[bit 9] BUSY : Busy bit
This bit indicates whether the sound generator is in operation. This bit is set to "1" upon the ST bit is set
to "1". It is reset to "0" when the ST bit is reset to "0" and the operation is completed at the end of one
tone cycle. Any write instructions performed on this bit has no effect.
[bit 8] DEC : Auto-decrement enable bit
The DEC bit is prepared for an automatic de-gradation of the sound in conjunction with the decrement
grade register.
If this bit is set to "1", the stored value in the amplitude data register is decremented by 1(one), every time
when the decrement counter counts the count of tone pulses from the toggle flip-flop specified by the
decrement grade register.
[bits 7 to 6] S1 to S0 : Operation clock select bits
These bits specify the clock input signal for the sound generator.
S1
0
0
1
1
[bit 5] TONE : Tone output bit
When this bit is set to "1", the SGO signal becomes a simple square-waveform (tone pulses) from the
toggle flip-flop. Otherwise it is the mixed (AND logic) signal of the tone and PWM pulses.
[bit 4] OE2 : Sound output enable bit
When this bit is set to "1", the external pin is assigned as the SGO output. Otherwise the pin can be used
as a general purpose I/O.
SOUND GENERATOR
15 14 13
TST — —
(R/W) — —
(0) — —
7 6 5
S1 S0 TONE
(R/W) (R/W) (R/W)
(0) (0) (0)
S0
0
1
0
1
20-5
12 11 10
— — —
— — —
— — —
4 3 2
OE2 OE1 INTE
(R/W) (R/W) (R/W)
(0) (0) (0)
Clock Input
Machine clock
1/2 Machine clock
1/4 Machine clock
1/8 Machine clock
← Bit No.
9 8
BUSY DEC SGCRH
(R) (R/W)
(0) (0)
← Bit No.
1 0
INT ST SGCRL
(R/W) (R/W)
(0) (0)