Fujitsu MB90420/5 (A) Series Hardware Manual page 14

Fig. 3.1 Oscillation Stabilization Wait Time of Evaluation Products/Flash and
Mask Products at Power-on Reset ............................................................................... 3-5
Fig. 3.2 Oscillation Stabilization Wait Time of Evaluation Products/Flash and
Mask Products at Power-on Reset ............................................................................... 3-6
Fig. 3.3 Block Diagram of Internal Reset ................................................................................... 3-7
Fig. 3.4 Block Diagram of External Reset Pin ........................................................................... 3-7
Fig. 3.5 Reset Operation Flow..................................................................................................... 3-8
Fig. 3.6 Transfer of Reset Vectors and Mode Data ................................................................... 3-9
Fig. 3.7 Block Diagram of Reset Factor Bit ............................................................................. 3-10
Fig. 3.8 Configuration of Reset Factor Bit (Watchdog Timer Control Register).................. 3-11
Fig. 4.1 Clock Supply Map........................................................................................................... 4-4
Fig. 4.2 Block Diagram of Clock Generation Section ............................................................... 4-5
Fig. 4.3 Configuration of Clock Select Register (CKSCR) ....................................................... 4-7
Fig. 4.3 Transition Diagram of Machine Clock Selection State ............................................. 4-11
Fig. 4.5 Operation Immediately After Oscillation Started ...................................................... 4-12
Fig. 4.6 Connection of Crystal or Ceramic Oscillator............................................................. 4-13
Fig. 4.7 Connection of External Clock ..................................................................................... 4-13
Fig. 5.1 CPU Operating Mode and Current Consumption........................................................ 5-3
Fig. 5.2 Block Diagram of Low-power Consumption Controller ............................................. 5-5
Fig. 5.3 Configuration of Low-power Consumption Mode Control Register (LPMCR) ......... 5-7
Fig. 5.4 Clock in CPU Intermittent Operation Mode ............................................................... 5-10
Fig. 5.5 Cancellation of Sleep Mode by Interrupt.................................................................... 5-13
Fig. 5.6 Cancellation of Timer Mode (External Reset) ............................................................ 5-16
Fig. 5.7 Cancellation of Stop Mode (External Reset).............................................................. 5-18
Fig. 5.8 State Transition Diagram ............................................................................................. 5-19
Fig. 6.1 General Flow of Interrupt Operation............................................................................. 6-4
Fig. 6.2 Interrupt Control Register (ICR00 to ICR15) at Writing .............................................. 6-8
Fig. 6.3 Interrupt Control Register (ICR00 to ICR15) at Reading............................................. 6-9
Fig. 6.4 Configuration of Interrupt Control Register (ICR)..................................................... 6-10
Fig. 6.5 Hardw are Interrupt Request during W riting to the Resource Control Register Area ... 6-14
Fig. 6.6 Operation of Hardware Interrupt................................................................................. 6-16
Fig. 6.7 Flow of Handling Processing ...................................................................................... 6-17
Fig. 6.8 Use Procedure for Hardware Interrupt ....................................................................... 6-18
Fig. 6.9 Example of Multiple Interrupts.................................................................................... 6-19
Fig. 6.10 Interrupt Processing Time ........................................................................................... 6-20
Fig. 6.11 Operation of Software Interrupt .................................................................................. 6-22
Fig. 6.12 Operation of EI2OS....................................................................................................... 6-24
Fig. 6.13 Configuration of EI2OS Descriptor (ISD) ................................................................... 6-25
Fig. 6.14 Configuration of Data Counter (DCT) ......................................................................... 6-26
Fig. 6.15 Configuration of I/O Register Address Pointer (IOA) ............................................... 6-26
Fig. 6.16 Configuration of EI2OS Status Register (ISCS) ........................................................ 6-27
Fig. 6.17 Configuration of Buffer Address Pointer (BAP) ........................................................ 6-28
Fig. 6.18 Operation Flow of EI2OS ............................................................................................. 6-29
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