Operation Of Time-Base Timer - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

9.4.2 Operation of Time-base Timer

The time-base timer has a timer function for the oscillation stabilization time wait for the clock source of
watchdog timer, main clock and PLL clock. It also has the interval interrupt function that generates interrupts
at a certain cycle.
n Operation of time-base timer
The time-base timer is composed of an 18-bit counter that uses 2-divided main original oscillation clock as
the count clock, and the time-base timer continues the count while the original oscillation is being input.
The time-base timer is cleared by a power-on reset, a transition to the stop mode, a transition from the main
clock mode to the PLL clock mode by the MCS bit of the CKSCR register, a transition from the main clock
mode to the sub-clock mode by the SCS bit of the CKSCR register, and by writing 0 to the TBR bit of the
TBTC register.
The watchdog timer function and the interval interrupt function that use the output of the time-base timer are
affected by clearing the time-base timer.
n Interval interrupt function
The interval interrupt function generates interrupts at a certain cycle by the carrying-up signal of the time-
base counter. The TBOF flag is set based on the interval time set for the TBC1 and 0 bits of the TBTC
register. The setting of this flag is determined based on the time when the time-base timer was last cleared.
When a transition is performed from the main clock mode to the PLL clock mode, the time-base timer is
cleared temporarily because it is used as the oscillation stabilization wait timer for PLL clock.
When a transition is performed to the stop mode, the TBOF flag is cleared concurrently with the mode
transition because the time-base timer is used as the oscillation stabilization time wait timer for at restoring.
n Time-base timer interrupt
When the time-base timer counter increments with the internal count clock, and an overflow occurs at the
selected interval timer bit, the interrupt request flag bit TBOF bit of TBTCregister is set to 1. At this time,
when the interrupt request enable bit is already enabled TBIE of TBTC register, an interrupt request (#35) is
issued to the CPU. Clear the interrupt request by writing 0 to the TBOF with the interrupt-processing routine.
The TBOF bit is set irrespective of the value of the TBIE bit when an overflow occurs at the specified bit.
Note: Clear the interrupt request flag bit (TBTC: TBOF) while the time-base timer interrupt is disabled by
the TBIE bit or by the ILM bit of the processor status (PS).
1. When the TBOF bit is 1 and the TBIE bit is changed from disable to enable (0 → 1), an
Remarks:
interrupt request is issued immediately.
2. The expansion intelligent I/O service (EI
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MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
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9-14
OS) cannot be used for the time-base timer.