Fig. 9.6 Clearing Timing And Watchdog Timer Interval Time - Fujitsu MB90420/5 (A) Series Hardware Manual

WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK)
n Watchdog timer interval time
Figure 9.6 shows the relationship between watchdog timer clearing timing and the watchdog timer interval
time. The interval time changes depending on the timing of the watchdog timer clearing, and requires 3.5 to
4.5 times of the count clock cycle.
[WDG Timer block diagram]
Clock
selector
WTE Bit
[Minimum interval time] When WTE bit is cleared immediately before rising edge of count clock
Counter cleared
Count clock a
2-divided value b
2-divided value c
Count enabled
Reset signal d
[Maximum interval time] When WTE bit is cleared immediately after rising edge of count clock
Counter cleared
Count clock a
2-divided value b
2-divided value c
Count enabled
Reset signal d
2-bit counter
a
2-divided
circuit
Enabling count
output circuit
WTE bit cleared
9 × (count clock cycle / 2)
WTE bit cleared

Fig. 9.6 Clearing Timing and Watchdog Timer Interval Time

b c
2-divided
Reset circuit
circuit
Count enabled and cleared
Count started
7 × (count clock cycle / 2)
Count started
9-13
d
Reset signal
Watchdog reset generated
Watchdog reset generated