Fujitsu MB90420/5 (A) Series Hardware Manual page 316

MB90420/5 (A) SERIES F
[Control register (SCR0/1)]
PEN : 0
P, SBL, A/D : These bits have no meaning.
CL : 1 (8-bit data)
REC : 0 (The error flags are cleared for initialization.)
RXE, TXE : At least one of these bits is 1.
[Status register (SSR0/1)]
RIE 1 : When interrupt used
0 : When interrupt not used
TIE 1 : When interrupt used
0 : When interrupt not used
• Starting communications
Communications are started by writing data to the output data register (SODR0/1). Note that even when
starting communications to receive data, always write temporary data to SODR.
• Terminating communications
When transmission/reception of one data frame is terminated, the RDRF flag of the status register
(SSR0/1) is set to 1. During reception, check the overrun error flag bit (SSR0/1: ORE) to confirm that
communications are performed normally.
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MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
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