Table 8-26 State Of Port 6 Pins - Fujitsu MB90420/5 (A) Series Hardware Manual

• Operation in stop mode or time-base timer mode
When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is
1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Because the output buffer is set forcibly to OFF. Input is fixed to prevent leakage due to opening of input.
Table 8-26 shows the state of the port 6 pins.
Pin Name
P60/AN0 to
P67/AN7
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
I/O PORT

Table 8-26 State of Port 6 Pins

Normal
Sleep Mode
Operation
General- General-
purpose I/O purpose I/O
port pin port pin
Stop Mode or
Time-base Timer
Mode (SPL = 0)
General-purpose
I/O port pin
8-35
Stop Mode or Time-
base Timer Mode
(SPL = 1)
Input cut off, and
output becomes Hi-Z