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14.4.1 LCDC Control Register Lower (LCRL)
The LCDC control register lower (LCRL) controls the driving power, selects display or display blanking, and
selects the display mode.
„
LCDC control register lower (LCRL)
Address
bit 7
bit 6
006C
CSS LCENVSEL BK MS1 MS0 FP1 FP0
H
R/W
R/W
R/W
: Both read and write
: Unused
X
: Undefined
: Initial value
LCD CONTROLLER/DRIVER
bit 5
bit 4
bit 3
bit 2
R/W
R/W
R/W
R/W
FP1
0
0
1
1
N: Time division count
Fc: Original oscillation
MS1
0
0
1
1
BK
0
1
VSEL
0
1
LCEN
0
1
CSS
0
1
Fig. 14.9 LCDC Control Register Lower (LCRL)
14-13
Initial value
bit 1
bit 0
00010000
R/W
R/W
Frame Cycle Select Bits
FP0
× N)
0
F
/ (2
C
13
× N)
1
F
/ (2
C
14
× N)
0
F
/ (2
C
15
× N)
1
F
/ (2
C
16
MS0
Display Mode Select Bits
0
Stops LCD operation
1
1/2 duty output mode (time division count N = 2)
1/3 duty output mode (time division count N = 3)
0
1/4 duty output mode (time division count N = 4)
1
Display/Display Blanking Select Bit
Display
Display blanking
LCD Driving Power Control Bit
Uses external split resistors
Uses internal split resistors
Timer Mode Operation Enable Bit
Stops operation in timer mode
Does not stop operation in timer mode
Clock Select Bit
Selects main clock
Selects sub-clock
B
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