Table 12-7 Function Of Each Bit Of Status Register (Ssr0/1) - Fujitsu MB90420/5 (A) Series Hardware Manual

Table 12-7 Function of Each Bit of Status Register (SSR0/1)

Bit Name
bit 15 PE: Parity error
flag bit
bit 14 ORE: Overrun
error flag bit
bit 13 FRE: Framing
error flag bit
bit 12 RDRF: Receive
data full flag bit
bit 11 TDRE: Transmit
data empty flag
bit
BDS: Transfer
bit 10
direction
selection bit
RIE: Receive
bit 9
interrupt request
enable bit
bit 8 TIE: Transmit
interrupt request
enable bit
• At reception, this bit is set to 1 at a parity error; it is cleared when 0 is written to the
REC bit of the mode register (SMR).
• When this bit and the RIE bit are 1, a receive interrupt request is output.
• When this flag is set, data of the input data register (SIDR) is invalid.
• At reception, this bit is set to 1 at an overrun error; it is cleared to 0 when 0 is written to
the REC bit of the mode register (SMR).
• When this bit and the RIE bit are 1, a receive interrupt request is output.
• When this flag is set, data of the input data register (SIDR) is invalid.
• At reception, this bit is set to 1 at a framing error; it is cleared to 0 when 0 is written to
the REC bit of the mode register (SMR).
• When this bit and the RIE bit are 1, a receive interrupt request is output.
• When this flag is set, data of the input data register (SIDR) is invalid.
• This bit is the flag indicating the state of the input data register (SIDR).
• When receive data is loaded into SIDR, this bit is set to 1. When SIDR is read, this bit
is cleared to 0.
• When this bit and the RIE bit are 1, a receive interrupt request is output.
• This bit is the flag indicating the state of the output data register (SODR).
• When transmit data is written to SODR, this bit is cleared to 0. When data is loaded
into the transmit shift register and transmission starts, this bit is set to 1.
• When this bit and the TIE bit are 1, a transmit interrupt request is output.
Note: At the initial state, this bit is set to 1 (indicating that SODR is unused).
• Bit to determine whether to transfer serial data starting at the least significant bit (LSB
first; BDS = 0) or transfer serial data starting at the most significant bit (MSB first, BDS
= 1).
Note: At reading from or writing to the serial-data register, when data is written to the
SDR register to interchange the upper side and lower side of data, the written
data is invalidated.
• Bit to enable/disable output of the receive interrupt request to the CPU.
• When this bit and the receive data flag bit (RDRF) are 1, or when this bit and at least
one of the error flag bits (PE, ORE, and FRE) are 1, a receive interrupt request is
output.
• Bit to enable/disable output of the transmit interrupt request to the CPU.
• When this bit and the TDRE bit are 1, a transmit interrupt request is output.
UART
Function
12-15