Fujitsu MB90420/5 (A) Series Hardware Manual page 341

• LCDC control register lower (LCRL)
This register controls the LCD drive power, selects display or display blanking, selects the display mode,
and selects the LCD clock cycle.
• LCDC control register higher (LCRH)
This register switches between segment output and the general-purpose port.
• Display RAM
This "16 × 8-bit" RAM generates segment output signals. Data in this RAM is read automatically in
synchronization with the common-signal selection timing, and output from the segment output pin.
• Prescaler
The prescaler generates the frame frequency by setting selected from four different frequencies.
• Timing controller
The timing controller controls common signals and segment signals, based on the frame frequency and the
LCRL register.
• AC generator
This circuit generates LCD driving AC waveform from the timing controller signals.
• Common driver
This is the driver for LCD common pins.
• Segment driver
This is the driver for LCD segment pins.
• Split resistors
Split resistors split and generate the LCD driving voltage. External split resistors can also be connected.
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Power supply voltage for LCD controller/driver
The power supply voltage for the LCD driver is set by either using internal split resistors or by connecting
split resistors to the V0 to V3 pins.
LCD CONTROLLER/DRIVER
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