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MB90420/5 (A) SERIES F
n Operation of software interrupt
Figure 6.11 shows the operation from generation of the software interrupt to completion of the interrupt
handling.
Internal bus
PS
: Processor status
I
: Interrupt enable flag
S
: Stack flag
IR
: Instruction register
(1) A software interrupt instruction is executed.
(2) After the necessary processing such as saving the dedicated registers according to the microcode
corresponding to the software interrupt instruction, branch processing is performed.
(3) The interrupt handling is terminated by the RETI instruction in the interrupt-processing routine of user.
Note:
When the program bank register (PCB) is FF
the table for the INT #vct8 instruction. A CALLV and INT #vct8 instructions can not use the same
address in creating a software.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
PS, PC . . .
(2) Microcode
RAM
Fig. 6.11 Operation of Software Interrupt
H
6-22
PS
(1)
IR
Queue
, the vector area for the CALLV instruction overlaps
I
S
Fetch
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