Status Register (Ssr0/1); Fig. 12.6 Status Register (Ssr0/1) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

12.4.3 Status Register (SSR0/1)

The status register (SSR0/1) checks the transmission/reception status and error status and enables/disables
interrupts.
n Status register (SSR0/1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
Address
CH0: 000037
H
PE ORE
CH1: 00003B
H
R
R/W : Both read and write
R : Read only

: Unused
X : Undefined
: Initial value
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
FRE RDRF TDRE BDS
R R R R
TIE
0
1
RIE
0
1
BDS
0
1
TDRE
0
1
RDRF
0
1
FRE
0
1
ORE
0
1
PE
0
1

Fig. 12.6 Status Register (SSR0/1)

bit 9 bit 8 bit 7
RIE TIE
R/W R/W R/W
Transmit Interrupt Request Enable Bit
Disables transmit interrupt request output
Enables transmit interrupt request output
Receive Interrupt Request Enable Bit
Disables receive interrupt request output
Enables receive interrupt request output
Transfer Direction Select Bit
LSB first (transfer starts at least significant bit)
MSB first (transfer starts at most significant bit)
Transmit Data Empty Flag Bit
With transmit data (writing of transmit data disabled)
No transmit data (writing of transmit data enabled)
Receive Data Full Flag Bit
No receive data
With receive data
Framing Error Flag Bit
No framing error
With framing error
Overrun Error Flag Bit
No overrun error
With overrun error
Parity Error Flag Bit
No parity error
With parity error
12-14
bit 0
Initial value
00001000
(SIDR/SODR)
B