Fig. 23.2 Node Status Transition Diagram; Table 23-6 Correspondence Between Ns1 And Ns0 And Node Status - Fujitsu MB90420/5 (A) Series Hardware Manual

[bits 9 to 8] NS1 and NS0: Node status bits 1 and 0
These bits indicate the current node status.

Table 23-6 Correspondence between NS1 and NS0 and Node Status

Note: Warning (error active) is included in the error active in CAN Specifications 2.0 B for the node
status, however, indicates that the transmit error counter or receive error counter has exceeded 96.
The node status change diagram is shown in Figure 23-6.
REC ≥ 128
TEC ≥ 128
Error
passive
[bit 7] TOE: Transmit output enable bit
Writing 1 to this bit switches from a general-purpose port pin to a transmit pin of the CAN controller.
0: General-purpose port pin
1: Transmit pin of CAN controller
[bit 2] NIE: Node status transition interrupt enable bit
This bit enables or disables a node status transition interrupt (when NT = 1).
0: Node status transition interrupt disabled
1: Node status transition interrupt enabled
[bit 0] HALT: Bus operation stop bit
This bit sets or cancels bus operation stop, or displays its state.
CAN CONTROLLER
NS1 NS0
0 0
0 1
1 0
1 1
REC ≥ 96
or
TEC ≥ 96
Warning
(Error active)
or
REC ≤ 128
or
TEC ≤ 128

Fig. 23.2 Node Status Transition Diagram

Node Status
Error active
Warning (error active)
Error passive
Bus off
Hardware reset
Error active
REC ≤ 96
or
TEC ≤ 96
TEC ≥ 256
23-13
REC: Receive error counter
TEC: Transmit error counter
After 0 has been written to the HALT bit
of the register (CSR), continueous 11-bit
High levels (recessive bits) are input
128 times to the receive input pin (RX).
Bus off