Fujitsu MB90420/5 (A) Series Hardware Manual page 15

Fig. 6.19 Use Procedure for EI2OS .............................................................................................6-30
Fig. 6.20 Stack Operation at Starting Interrupt Handling .........................................................6-34
Fig. 6.21 Stack Area......................................................................................................................6-35
Fig. 7.1 Classification of Mode ....................................................................................................7-3
Fig. 7.2 Configuration of Mode Data ...........................................................................................7-5
Fig. 7.3 Relationship betw een Access Areas and P hysical Addresses in Single-chip M ode .7-6
Fig. 8.1 Block Diagram of Pins of Port 0 ....................................................................................8-7
Fig. 8.2 Block Diagram of Pins of Port 1 ..................................................................................8-12
Fig. 8.3 Block Diagram of Pins of Port 3 ..................................................................................8-17
Fig. 8.4 Block Diagram of Pins of Port 4 ..................................................................................8-22
Fig. 8.5 Block Diagram of Pins of Port 5 ..................................................................................8-27
Fig. 8.6 Block Diagram of Pins of Port 6 ..................................................................................8-32
Fig. 8.7 Block Diagram of Pins of Port 7 ..................................................................................8-37
Fig. 8.8 Block Diagram of Pins of Port 8 ..................................................................................8-42
Fig. 8.9 Block Diagram of Pins of Port 9 ..................................................................................8-47
Fig. 8.10 Eight-segment LED Connection Example ..................................................................8-51
Fig. 9.1 Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer .................9-4
Fig. 9.2 Watchdog Timer Control Register (WDTC) ..................................................................9-6
Fig. 9.3 Time-base Timer Control Register (TBTC) ...................................................................9-8
Fig. 9.4 Watch Timer Control Register .......................................................................................9-9
Fig. 9.5 Watchdog Timer Operation ..........................................................................................9-12
Fig. 9.6 Clearing Timing and Watchdog Timer Interval Time .................................................9-13
Fig. 9.7 Operation of Time-base Timer .....................................................................................9-18
Fig. 10.1 Block Diagram of 16-bit Reload Timer ........................................................................10-5
Fig. 10.2 Block Diagram of Pins of 16-bit Reload Timer ...........................................................10-7
Fig. 10.3 Registers for 16-bit Reload Timer................................................................................10-8
Fig. 10.4 Timer Control Status Register (upper) (TMCSR0/1H)................................................10-9
Fig. 10.5 Timer Control Status Register (lower) (TMCSR0/1L)...............................................10-11
Fig. 10.6 16-bit Timer Register (TMR0/1) ..................................................................................10-13
Fig. 10.7 16-bit Reload Register (TMRLR0/1L, TMRLR0/1H)...................................................10-14
Fig. 10.8 Setting of Internal Clock Mode ..................................................................................10-16
Fig. 10.9 Setting of Event Counter Mode..................................................................................10-16
Fig. 10.10 State Transition Diagram of Counter ........................................................................10-17
Fig. 10.11 Count Operation in Reload Mode (Operation of Software Trigger) .......................10-18
Fig. 10.12 Count Operation in Reload Mode (Operation of External Trigger) ........................10-19
Fig. 10.13 Count Operation in Reload M ode (Operation of Softw are Trigger and G ate Input) ....10-19
Fig. 10.14 Count Operation in One-shot Mode (Operation of Software Trigger)....................10-20
Fig. 10.15 Count Operation in One-shot Mode (Operation of External Trigger).....................10-21
Fig. 10.16 Count Operation in One-shot Mode (Operation of Software Gate Input) ..............10-21
Fig. 10.17 Count Operation in Reload Mode (Operation of Event Count Mode) ....................10-22
Fig. 10.18 Count Operation in One-shot Mode (Operation of Event Count Mode).................10-23
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