Fujitsu MB90420/5 (A) Series Hardware Manual page 394

n Sample program for DTP function
• Processing specification
– Channel 0 of the EI
– RAM data is output to port 0 by performing DTP processing (EI
n Sample coding
ICR02 EQU
DDR0 EQU
DDR5 EQU
ENIR EQU
EIRR EQU
ELVRL EQU
ELVRH EQU
ER0 EQU
EN0 EQU
BAPL EQU
BAPM EQU
BAPH EQU
ISCS EQU
IOAL EQU
IOAH EQU
DCTL EQU
DCTH EQU
;---------- Main program ----------------------------------------------------
-------
CODE CSEG
START:
;
MOV
MOV
AND
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
CLRB
MOV
CLRB
SETB
MOV
OR
LOOP: MOV
MOV
BRA
DTP/EXTERNAL INTERRUPT CIRCUIT
2
OS is started by detecting the H level of the signal input to the INT0 pin.
; Interrupt control register for DTP/external interrupt circuit
0000B2
H
; Port 0 direction register
000010
H
; Port 5 direction register
000015
H
; DTP/Interrupt enable register
000030
H
; DTP/Interrupt factor register
000031
H
; Request level setting register
000032
H
; Request level setting register
000033
H
; INT0 interrupt flag bit
EIRR:0
; INT0 interrupt enable bit
ENIR:0
; Buffer address pointer lower
000100
H
; Buffer address pointer middle
000101
H
; Buffer address pointer higher
000102
H
; EI2OS status register
000103
H
; I/O address register lower
000104
H
; I/O address register higher
000105
H
; Data counter lower
000106
H
; Data counter higher
000107
H
I:DDR0, #11111111
I:DDR5, #00000000
CCR, #0BFH
I:ICR02, #08
H
BAPL, #00
H
BAPM, #06
H
BAPH, #00
H
ISCS, #12
H
IOAL, #00
H
IOAH, #00
H
DCTL, #0A
H
DCTH, #00
H
I:EN0
I:ELVR, #00000001
I:ER0
I:EN0
ILM, #07
H
CCR, #40
H
A, #00
H
A, #01
H
LOOP
2
OS).
; Stack pointer (SP), etc., already initialized
; DDR0 set to output
B
; DDR5 set to input
B
; Interrupts disabled
; Interrupt level 0 (highest)
2
; EI OS enabled, channel 0
; Address of output data set
;
;
; Byte transfer performed and I/O address fixed
; Buffer address + 1 and transfer performed from memory
to I/O
; Destination address pointer
; Port 0 (PDR0) specified as transfer
; Transfer count = 10
;
; INT0 disabled using ENIR
; H level selected for INT0
B
; INT0 interrupt factor cleared using EIRR
; INT0 enabled using ENIR
; ILM in PS set to level 7
; Interrupts enabled
; Endless loop
;
;
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