Table 19-5 Function Of Each Bit Of A/D Control Status Register Lower (Adcsl) - Fujitsu MB90420/5 (A) Series Hardware Manual

F2mc-16lx family 16-bit microcontrollers
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MB90420/5 (A) SERIES F

Table 19-5 Function of Each Bit of A/D Control Status Register Lower (ADCSL)

Bit Name
bit 7
MD1, MD0:
bit 6
A/D conversion
mode select
bits
bit 5
ANS2, ANS1,
bit 4
ANS0:
bit 3
A/D conversion
start channel
select bits
bit 2
ANE2, ANE1,
bit 1
ANE0:
bit 0
A/D conversion
end channel
select bits
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
• These bits select the conversion mode used when the A/D conversion function is used.
• Using the values of the MD1 and MD0 bits, one of the following modes is selected: one-
shot conversion mode 1, one-shot conversion mode 2, continuous conversion mode 2, and
pause-convert mode.
• The meaning of each mode is shown below:
Single-shot conversion mode 1 :
One-shot conversion mode 2
Continuous conversion mode :
Pause-convert mode
Note: In the one-shot conversion, continuous conversion, and suspend-and-then-convert
modes, a restart caused by an external software trigger cannot be performed during
operation.
• These bits set the start channel for which A/D conversion is performed and check the
channel number for which A/D conversion is currently being performed.
• A/D conversion is started at the channel specified by these bits.
• During A/D conversion, the number of the channel for which A/D conversion is currently
being performed can be read. During suspension in the pause-conversion mode, the
number of the channel converted just previously can be read.
• These bits set the A/D conversion end channel.
• A/D conversion is started up to the channel specified by these bits.
• When the same channel as specified for the ANS2 to ANS0 bits is specified for the ANE2 to
ANE0 bits, only that channel is converted.
Also, in the continuous conversion mode or the pause-conversion mode, when conversion
for up to the channel specified by these bits ends, a return is made to the start channel
specified by the ANS2 to ANS0 bits. When the specified channel is "the start channel > the
end channel", the start channel to the AN7 channel are converted and then the AN0
channel to the end channel are converted, ending the first A/D conversion.
Function
A/D conversion is performed continuously only once for
the channel specified for ANS2 to ANS0 to the channel
specified for ANE2 to ANE0. A restart can be performed
during operation.
:
A/D conversion is performed continuously only once for
the channel specified for ANS2 to ANS0 to the channel
specified for ANE2 to ANE0. A restart cannot be made
during operation.
A/D conversion is performed continuously repeatedly for
the channel specified for ANS2 to ANS0 to the channel
specified for ANE2 to ANE0 until it is forcibly stopped
using the BUSY bit. A restart cannot be performed
during operation.
:
A/D conversion is performed for the channel specified for
ANS2 to ANS0 to the channel specified for ANE2 to
ANE0 for each channel until it is forcibly stopped using
the BUSY bit. A restart cannot be performed during
operation. A restart during suspension of the operation
is caused by the start factor specified for the STS1/0
bits.
19-12

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