Operation Of Watchdog Timer; Fig. 9.5 Watchdog Timer Operation - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

9.4.1 Operation of Watchdog Timer

The watchdog timer issues a reset request when 0 is not written to the WTE bit of the WDTC register within
the predetermined time due to software nullfunction or hardware upset of program.
n Start of watchdog timer
The watchdog timer is started when 0 is written to the WTE bit of the WDTC register when the watchdog
timer is stopped. At this point, the reset interval for the watchdog timer is set simultaneously by the WT1 and
0 bits. The reset interval setting is valid only for data written at starting the watchdog timer.
n Block of watchdog timer reset
When the watchdog timer is started, the 2-bit watchdog counter must be cleared periodically during program
execution. To be more specific, 0 must be written to the WTE bit of the WDTC register. The watchdog
counter is composed of the 2-bit counter using the carrying-up signal of the time-base timer as the clock
source. So, when the time-base timer is cleared, the watchdog reset occurrence time may become longer
than the setting.
Time-base
Watchdog
WTE write
n Stop of watchdog timer
The watchdog timer is stopped by various reset factors.
n Clear of watchdog timer
The watchdog timer is cleared by writing to the WTE bit, by causing a reset, and by transitions to the sleep
mode, stop mode, or timer mode.
During the timer mode, the watchdog timer counter is cleared and the count is stopped.
n Check of reset factors
The reset factors can be indicated by checking bits of the PONR, WRST, ERST, and SRST of the watchdog
timer control register (WDTC) after a reset.
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MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
00 01 10
Watchdog started Watchdog cleared

Fig. 9.5 Watchdog Timer Operation

9-12
00 01 10
Watchdog reset generated
11 00