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[bits 11, 10] CKS1, CKS0: Counter clock select bits
These bits select the count clock for the 16-bit decrement counter. They cannot be rewritten during
operation.
[bit 9] PGMS: PPG output mask select bit
When 1 is written to this bit, the PPG output can be masked to 0 or 1 irrespective of the mode setting,
cycle setting value, and duty setting.
PPG output when 1 written to PGMS
To output the inverted value of the above mask value (all Hs when normal polarity specified, or all Ls
when reverse polarity specified), write the same value to the cycle setting register and the duty setting
register.
[bit 8] Unused bit
Always write 0 to this bit.
[bits 7, 6] EGS1, EGS0: Trigger input edge select bits
Whichever mode is selected, the software trigger is enabled when 1 is written to the software trigger bit.
[bit 5] IREN: Interrupt request enable bit
This is the interrupt enable bit for the PPG timer. When this bit is 1, an interrupt occurs when the interrupt
flag (bit 4: IRQF) is set to 1.
[bit 4] IRQF: Interrupt request flag
When bit 5 (IREN) is enabled and the interrupt factor specified for bits 3 and 2 (IRS1 and IRS0) occurs,
this bit (IRQF) is set, issuing an interrupt request to the CPU.
This bit is both read and write. It is cleared only when 0 is written to it; writing 1 does not change its bit
value. The bit value read from this bit using a read-modify-write instruction is always 1, irrespective of the
bit value.
PPG TIMER
CKS1
CKS0
0
0
0
1
1
0
1
1
φ: Machine clock
Polarity
Normal polarity
Invert polarity
EGS1
EGS0
0
0
0
1
1
0
1
1
0
Disables interrupt
1
Enables interrupt
Cycle
φ (Initial value)
φ/4
φ/16
φ/64
PPG Output
L
H
Edge Selection
Invalid
(initial value)
Rising edge
Falling edge
Both edges
(initial value)
13-7
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