Table of Contents
Advertisement
• Clock selector
The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external
input clock, and internal clock (clock supplied from 16-bit reload timer).
• Receive controller
The receive controller is composed of the receive bit counter, start bit detection, and receive parity counter.
The receive bit counter counts the receive data, and issues a receive interrupt request when reception of
one piece of data is completed according to the set data length. The start bit detection detects the start bit
in the serial input signal; when the detection detects the start bit, the detection writes data to the SIDR
while transferring data according to the set transfer rate. The receive parity counter calculates the parity of
the receive data.
• Transmit controller
The transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity
counter. The transmit bit counter counts the transmit data, and issues a transmit interrupt request when
reception of one piece of data is completed according to the set data length. The transmit start circuit
starts transmission when SODR is written. The transmit parity counter generates the parity bit of the data
transferred when parity is provided.
• Receive shift register
The receive shift register writes the receive data input from the SIN0 pin while shifting bit-by-bit, and when
the data reception is completed, transfers the receive data to the SIDR register.
• Transmit shift register
Data written to SODR is transferred to the transmit shift register, and then the data is output to the SOT0
pin while shifting bit-by-bit.
• Mode register (SMR0/1)
The mode register performs the following: selecting operation mode, selecting clock input source, setting
dedicated baud rate generator, selecting clock rate (clock division value) when dedicated baud rate
generator used, enabling/disabling output to serial-data pin, and enabling/disabling output to clock pin.
• Control register (SCR0/1)
The control register performs the following: setting parity, selecting parity, setting stop bit length, setting
data length, selecting frame data format in mode 1, clearing flag, enabling/disabling transmission, and
enabling/disabling reception.
• Status register (SSR0/1)
The status register checks the transmit/receive state and error state and sets enabling/disabling of the
transmit/receive interrupt request.
• Input data register (SIDR0/1)
The input data register holds the receive data. The serial input is converted and then stored in this
register.
• Output data register (SODR0/1)
The output data register sets the transmit data. Data written to this register is serial-converted and then
output.
UART
12-7
Advertisement
Table of Contents
