A/D Data Register (Adcrh/ Adcrl); Fig. 19.6 A/D Data Register (Adcrh/ Adcrl) - Fujitsu MB90420/5 (A) Series Hardware Manual

19.4.3 A/D Data Register (ADCRH/ ADCRL)

The A/D data registers (ADCRH/ ADCRL) store the results of A/D conversion and also select the A/D
conversion resolution.
n A/D data register (ADCRH/ ADCRL)
bit 15 bit 14bit 13bit1 2 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
000023
H
S10 ST1 ST0 CT1 CT0
000022
H
W W W
8-/10-BIT A/D CONVERTER
— D9 D8
W W — R R
D0 to D9
Converted data
CT1 CT0
0 0
0 1
1 0
1 1
ST1 ST0
0 0
0 1
1 0
1 1
S10
0 10-bit resolution mode (D9 to D0)
1 8-bit resolution mode (D7 to D0)

Fig. 19.6 A/D Data Register (ADCRH/ ADCRL)

D7 D6 D5 D4
R R R R
A/D Data Bits
Compare Time Setting Bits
44 machine cycles (5.50 µs @ 8 MHz)
66 machine cycles (4.12 µs @ 16 MHz)
88 machine cycles (5.50 µs @ 16 MHz)
176 machine cycles (11.0 µs @ 16 MHz)
Sampling Time Setting Bits
20 machine cycles (2.5 µs @ 8 MHz)
32 machine cycles (2.0 µs @ 16 MHz)
48 machine cycles (3.0 µs @ 16 MHz)
128 machine cycles (8.0 µs @ 16 MHz)
A/D Data Bit
19-13
Initial value
D3 D2 D1 D0 00101XXX
R R R R XXXXXXXX
B
B