Fujitsu MB90420/5 (A) Series Hardware Manual page 11

23.6.11 Transmission Cancel Register (TCANR) ...............................................................23-21
23.6.12 Transmission Complete Register (TCR)................................................................23-22
23.6.13 Transmission Interrupt Enable Register (TIER)....................................................23-22
23.6.14 Reception Complete Register (RCR) .....................................................................23-23
23.6.15 Remote Request Receive Register (RRTRR) ........................................................23-23
23.6.16 Receive Overrun Register (ROVRR) ......................................................................23-24
23.6.17 Reception Interrupt Enable Register (RIER) .........................................................23-24
23.6.18 Acceptance Mask Select Register (AMSR) ...........................................................23-25
23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .....................................23-26
23.6.20 Message Buffers ......................................................................................................23-27
23.6.21 ID Register x (x = 0 to 15) (IDRx) ............................................................................23-28
23.6.22 DLC Register x (x = 0 to 15) (DLCRx).....................................................................23-29
23.6.23 Data Register x (x = 0 to 15) (DTRx).......................................................................23-30
23.6.24 CAN WAKE UP Control Register (CWUCR) ..........................................................23-31
23.7 Transmission of CAN Controller .......................................................................................23-32
23.8 Reception of CAN Controller .............................................................................................23-34
23.9 Reception Flowchart for CAN Controller..........................................................................23-36
23.10 How to Use CAN Controller ...............................................................................................23-37
23.11 Procedure for Transmission by Message Buffer (x) .......................................................23-38
23.12 Procedure for Reception by Message Buffer (x) .............................................................23-40
23.13 Setting Configuration of Multi-level Message Buffer ......................................................23-41
23.14 CAN WAKE UP Function ....................................................................................................23-43
Chapter 24 Low Voltage and CPU Operation Detection Reset Circuit............................ 24-1
24.1 Overview of Low Voltage and CPU Operation Detection Reset Circuit ..........................24-3
24.2 Configuration of Low Voltage and CPU Operation Detection Reset Circuit...................24-4
24.3 Register for Low Voltage and CPU Operation Detection Reset Circuit ..........................24-5
24.4 Operation of Low Voltage and CPU Operation Detection Reset Circuit .........................24-7
24.5 Cautions when Using Low Voltage and CPU Operation Detection Reset Circuit ..........24-8
24.6 Sample Program for Low Voltage and CPU Operation Detection Reset Circuit ............24-9
Chapter 25 1-Mbit Flash Memory ...................................................................................... 25-1
25.1 Overview of 1-Mbit Flash Memory.......................................................................................25-3
25.2 Block Diagram for Entire Flash Memory and Flash Memory Sector Configuration ......25-4
25.3 Program/Erase Mode............................................................................................................25-6
25.4 Flash Memory Control Status Register (FMCS).................................................................25-8
25.5 Start Automatic Algorithm of Flash Memory ...................................................................25-10
25.6 Check Execution State of Automatic Algorithm..............................................................25-11
25.6.1 Data Polling Flag (DQ7) ...........................................................................................25-12
25.6.2 Toggle Bit Flag (DQ6) ..............................................................................................25-13
25.6.3 Timing Limit Exceeding Flag (DQ5) .......................................................................25-14
25.6.4 Sector Erase Timer Flag (DQ3)...............................................................................25-15
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