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MB90420/5 (A) SERIES F
6.4.5 Hardware Interrupt Handling Time
From issuance of the hardware interrupt request to execution of the interrupt-processing routine, it requires
the time for the currently executing instruction to be terminated plus the interrupt handling time.
n Hardware interrupt handling time
From issuance and acceptance of the hardware interrupt-processing routine, it requires the interrupt request
sample wait and the interrupt handling time (time required for preparation for interrupt processing). Figure
6.10 shows the interrupt processing time.
Operation of CPU
Interrupt wait time
Interrupt request issued
: Last instruction cycle where interrupt request sampled
*
: One machine cycle is equal to one cycle of the machine clock (φ).
• Interrupt request sample wait time
It indicates the duration from the issuance of the interrupt request to the termination of the currently
executing instruction.
interrupt request in the last cycle of each instruction. As a result, the CPU cannot recognize the interrupt
request during execution of each instruction, and wait time occurs.
The interrupt request sample wait time is longest when the interrupt request is issued immediately after
starting execution of the POPW, RW0, ...RW7 instructions with the longest execution cycle (45 machine
cycles).
• Interrupt handling time (θ machine cycles)
The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the
system stack and fetch the interrupt vectors after accepting the interrupt request. The interrupt handling
time is obtained using the following equations.
At interrupt start: θ = 24 + 6 × Z machine cycles
At interrupt return: θ = 11 + 6 × Z machine cycles (RETI instruction)
The interrupt handling time depends on the address indicated by the stack pointer. Table 6-9 shows the
compensation value (Z) of the interrupt-handling time.
Table 6-9 Compensation Value (Z) of Interrupt Handling Time
External 8 bits
External even address
External odd address
Internal even address
Internal odd address
Remark: One machine cycle is equal to one clock cycle of the machine clock (φ).
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
Execution of normal
instruction
Interrupt request
sample wait time
Fig. 6.10 Interrupt Processing Time
Whether the interrupt request is issued or not is determined by sampling the
Address Indicated by Stack Pointer
Interrupt handling
Interrupt handling time
(θ machine cycle)*
Compensation Value (Z)
+4
+1
+4
+2
6-20
Interrupt-processing
routine
0
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