Clock Mode - Fujitsu MB90420/5 (A) Series Hardware Manual

4.4 Clock Mode

There are two clock modes: Main clock mode, PLL clock mode, and sub-clock mode.
n Main clock mode, PLL clock mode and sub-clock mode
• Main clock mode
The main clock mode uses the 2-divided oscillation clock, as the operating clock for the CPU and
resources, to stop the PLL clock.
• PLL clock mode
The PLL clock mode uses the PLL clock as the operating clock for the CPU and resources. The PLL clock
multiplication rate can be selected using the clock select register (CKSCR: CS1, CS0).
• Sub-clock mode
The Sub-clock mode uses the 4-divided sub-clock as the operating clock for the CPU and resources, to
stop the main clock and PLL clock.
n Transition of clock mode
Writing to the MCS bit and SCS bit of the clock select register (CKSCR) switches the clock mode to the main
clock mode, the PLL clock mode, or sub-clock mode.
• Transition from main clock mode to PLL clock mode
When the MCS bit of the CKSCR is rewritten from 1 to 0 in the main clock mode, the main clock switches
to the PLL clock after the oscillation stabilization wait time (2
• Transition from PLL clock mode to main clock mode
When the MCS bit of the CKSCR is rewritten from 0 to 1 in the PLL clock mode, the PLL clock switches to
the main clock when the edge of the PLL clock matches the edge of the main clock (after 1 to 8 PLL
clocks).
• Transition from main clock mode to sub-clock mode
When the SCS bit of the CKSCR is rewritten from 1 to 0 in the main clock mode, the main clock switches
to the sub-clock.
• Transition from sub-clock mode to main clock mode
When the SCS bit of the CKSCR is rewritten from 0 to 1 in the sub-clock mode, the sub-clock switches to
the main clock after the main clock oscillation stabilization wait time has elapsed.
stabilization wait time is selected using the WS1 bit or WS0 bit of the CKSCR.
• Transition from PLL clock mode to sub-clock mode
When the SCS bit of the CKSCR is rewritten from 1 to 0 in the PLL clock mode, the PLL clock switches to
the sub-clock.
• Transition from sub-clock mode to PLL clock mode
When the SCS bit of the CKSCR is rewritten from 0 to 1 in the sub-clock mode, the sub-clock switches to
the PLL clock after the main clock oscillation stabilization wait time has elapsed.
stabilization wait time is selected using the WS1 bit or WS0 bit of the CKSCR.
CLOCK
14
/HCLK) for the PLL clock.
4-9
The oscillation
The oscillation