Fig. 9.7 Operation Of Time-Base Timer - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F
n Operation of time-base timer
The operation of the following states is shown in Figure 9.7.
• At power-on reset
• At transition to sleep mode during operation of interval timer function
• At transition to stop mode
• When counter clear request issued
At a transition to the stop mode, the time-base timer is cleared and operation is stopped. At a return from
the stop mode, the oscillation stabilization wait time is counted using the time-base timer.
Counter value
3FFFF
Oscillation
stabilization wait
time overflow
00000
H
Power-on reset
(option)
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
STP bit
(LPMCR register)
When interval time select bits of time-base timer control register (TBTC: TBC1, TBC0) set
19
to 11 (2 /HCLK)
B
: Oscillation stabilization wait time
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
H
CPU operation
(TBTC: TBC1, TBC0 = 11
started
Cleared by interrupt-
Sleep cancelled by interval interrupt

Fig. 9.7 Operation of Time-base Timer

Cleared by transition
to stop mode
Interval cycle
processing routine
Sleep
Stop cancelled by external interrupt
9-18
Counter cleared
)
(TBTC:TBR = 0)
H
Stop