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MB90420/5 (A) SERIES F
n ROM correction address register (PADR0/PADR1)
These registers hold the addresses for the comparison with program counter. If there is a match and the
corresponding ADCSR compare enable bit is '1', this module demands the CPU to execute the INT9
instruction.
If the corresponding interrupt enalble bit is '0', nothing will occur even if there is a match.
PADR0 address: 1FF2
PADR1 address: 1FF5
The correspondance to the PASCR will be as follows.
ROM Correction Address Register
n ROM correction control register (PACSR)
Address: 00009E
H
Read/write →
Initial value →
This register controls operation of the address detect function and indicates its status.
[bits 7 to 4]
These are the reserved bits, always write '0'.
[bit 3] AD1E (Compare Enable 1)
This is the PADR1 enable bit.
When this bit is '1', this module compares the PADR1 register and the address. If there is the INT9
instruction is sent to the CPU.
[bit 2]
Reserved bit, always write '0'.
[bit 1] AD0E (Compare Enable 0)
This is the PADR0 enable bit.
When this bit is '1', this module compares the PADR0 register and the program counter. If there is a
match, the INT9 instruction is sent to the CPU.
[bit 0]
Reserved bit, always write '0'.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
byte
/1FF1
/1FF0
H
H
H
/1FF4
/1FF3
H
H
H
PADR0
PADR1
7
6
5
Reserved
Reserved
Reserved
(—)
(—)
(—)
(—)
(—)
(—)
21-4
byte
byte
Compare Enable Bit
AD0E
ED1E
4
3
2
AD1
Reserved
Reserved
(—)
(R/W)
(—)
(—)
(0)
(—)
Access
Initial value
R/W
undefined
R/W
undefined
← Bit No.
1
0
AD0
PACSR
Reserved
(R/W)
(—)
(0)
(—)
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