Table 19-4 Function Of Each Bit Of A/D Control Status Register Higher (Adcsh) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

Table 19-4 Function of Each Bit of A/D Control Status Register Higher (ADCSH)

Bit Name
bit 15 BUSY:
Conversion-in-
progress
indication bit
bit 14 INT:
Interrupt request
flag bit
bit 13 INTE:
Interrupt request
enable bit
bit 12 PAUS:
Pause flag bit
bit 11 STS1, STS0:
A/D start factor
bit 10
select bits
bit 9 STRT:
A/D conversion
start bit
RESV:
bit 8
Reserved bit
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
• This bit indicates the A/D converter operation.
• When this bit is 0 at read, it indicates that A/D conversion is stopped. When this bit is
1 at read, it indicates that A/D conversion is currently being performed.
• Writing 0 to this bit forcibly stops A/D conversion. Writing 1 to this bit does not change
this bit and does not affect other bits.
Note: Do not perform the following concurrently: forcibly stopping A/D conversion and
starting A/D conversion by software (BUSY = 0, STRT = 1).
• When the A/D conversion sets data in the A/D data register, this bit is set to 1.
• When this bit and the interrupt request enable bit (ADCSH: INTE) are 1, an interrupt
request is issued. At this time, when EI
• Writing 0 to this bit clears this bit. Writing 1 to this bit does not change this bit and
does not affect other bits.
• When EI
2
OS is started, this bit is cleared.
Note: Write 0 to this bit while A/D conversion is stopped.
• This bit enables/disables output of interrupts to the CPU.
• When this bit and the interrupt request flag bit (ADCSH: INT) are 1, an interrupt
request is issued.
• When using EI
2
OS, set this bit to 1.
• This bit is set to 1 when A/D conversion pauses.
• This A/D converter has only one A/D data register, so when reading of the old
conversion result by the CPU is not completed when the continuous conversion mode
is used, the old converted data is lost due to the writing of the new conversion result.
Therefore, when using the continuous conversion mode, basically EI
automatic transfer of the conversion result to memory each time conversion ends is
required. However, it can be assumed that transfer of converted data is not completed
before the next conversion is started at multiple interrupts, etc. This bit deals with this
situation; it is set to 1 until the value of the data register is transferred using EI
after conversion is completed; while this bit is 1, the next A/D conversion is stopped
and the next conversion data is not stored. Then, when transfer is completed, the A/D
converter automatically restarts conversion.
Note: This bit is only enable when EI
• These bits select the start factor for A/D conversion.
• When there are two or more start factors for A/D conversion, the first start factor is
used.
Note: The start factor is changed concurrently with rewriting. When rewriting during
A/D conversion, do so under when there is no targeted start factor.
• This bit starts A/D conversion by software.
• When 1 is written to this bit, A/D conversion is started.
• In the pause-convert mode, this bit does not cause a restart.
Note: Do not concurrently stop A/D conversion forcibly and start A/D conversion by
software (BUSY = 0, STRT = 1).
Note: Always write 0 to this bit.
Function
2
OS is already enabled, EI
2
OS is used.
19-10
2
OS is started.
2
OS and
2
OS