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n Oscillation stabilization wait time
• Oscillation stabilization wait time for oscillation clock
In the stop mode, the oscillator for the original oscillation stops, so the oscillation stabilization wait time is
required. The oscillation stabilization wait time is taken for the selected time by the WS1 and WS0 bits of
the clock select register (CKSCR). Setting 00
mode.
• Oscillation stabilization wait time for PLL clock
At a transition from a mode in which the CPU is operating on the main clock and the PLL clock is stopped
to a mode in which the CPU or a resource operates on the PLL clock, a transition is performed to the PLL
clock oscillation stabilization wait state, in which the CPU or resource operates on the main clock during
the oscillation stabilization wait.
The oscillation stabilization wait time for the PLL clock is fixed to 2
LOW-POWER CONSUMPTION MODE
to the WS1 and WS0 bits is allowed only in the main clock
B
5-23
14
/HCLK (HCLK: oscillation clock).
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