Overview Of Delayed Interrupt Generate Module; Fig. 17.1 Block Diagram Of Delayed Interrupt Generate Module - Fujitsu MB90420/5 (A) Series Hardware Manual

This chapter explains function and operation of the delayed interrupt generate module.

17.1 Overview of Delayed Interrupt Generate Module

The delayed interrupt generate module generates the interrupt for task switching. The interrupt request to
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the CPU of the F MC-16LX can be issued/cancelled by software using this module.
n Block diagram of delayed interrupt generate module
Figure 17.1 shows the block diagram of the delayed interrupt generate module.
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F MC-16LX Bus

Fig. 17.1 Block Diagram of Delayed Interrupt Generate Module

n Register for delayed interrupt generate module
The configuration of the register for the delayed interrupt generate module [delayed interrupt factor
generate/cancel register (DIRR: Delayed Interrupt Request Register)] is shown below.
DIRR address: 00009F
At a reset, the factor cancel state occurs.
DIRR is a register to control generation/cancellation of the delayed interrupt request. When 1 is written to
the register, the delayed interrupt request is issued. When 0 is written to the register, the delayed interrupt
request is cancelled. At a reset, the request cancel state occurs. Both 0 and 1 can be written to the
reserved bits, but for future extension, it is recommended to use the set bit instruction or clear bit instruction
when accessing this register.
DELAYED INTERRUPT GENERATE MODULE
Delayed interrupt factor generation/cancellation
bit 15 14
— —
H
Factor latch
13 12 11
— — —
17-3
10 9 8
— — R0
Initial value
-------0
B