System Overview And Architecture; Ptx5000 Packet Transport Router Description - Juniper PTX5000 Hardware Manual

CHAPTER 1

System Overview and Architecture

PTX5000 Packet Transport Router Description

Copyright © 2017, Juniper Networks, Inc.
PTX5000 Packet Transport Router Description on page 3
PTX5000 Hardware Component Overview on page 5
PTX5000 Component Redundancy on page 8
PTX5000 System Architecture Description on page 9
PTX5000 Packet Forwarding Engine Architecture on page 10
The PTX5000 Packet Transport Router is designed for large networks and network
applications, such as those supported by ISPs. The PTX5000 accommodates up to eight
Flexible PIC Concentrators (FPCs), each of which can be configured with a variety of
network media types.
The system architecture cleanly separates control operations from packet forwarding
operations. This design eliminates processing and traffic bottlenecks, permitting the
PTX5000 to achieve high performance.
Control operations are performed by the host subsystem, which runs the Junos operating
system (Junos OS) to handle routing protocols, traffic engineering, policy, policing,
monitoring, and configuration management.
Forwarding operations are performed by the Packet Forwarding Engines, which consist
of hardware, including ASICs, designed by Juniper Networks. The application-specific
integrated circuits (ASICs) are a definitive part of the hardware design and enable the
PTX5000 to achieve data forwarding rates that match current fiber-optic capacity.
For the forwarding capacity of each supported FPC, see
PTX5000" on page 97.
Figure 1 on page 4 and Figure 2 on page 5
"FPCs Supported on the
illustrate the front and rear of a PTX5000.
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