Motorola MPC8260 PowerQUICC II User Manual page 130

Part I. Overview
Internal
Abbreviation
Address
11A08 PSMR1
11A0A Reserved
11A0C TODR1
11A0E DSR1
11A10 SCCE1
11A14 SCCM1
11A17 SCCS1
11A18Ð11A1F Reserved
11A20 GSMR_L2
11A24 GSMR_H2
11A28 PSMR2
11A2A Reserved
11A2C TODR2
11A2E DSR2
11A30 SCCE2
11A34 SCCM2
11A37 SCCS2
11A38Ð11A3F Reserved
3-10
Table 3-1. Internal Memory Map (Continued)
Name
SCC1 protocol-speciÞc mode register
Ñ
SCC1 transmit-on-demand register
SCC1 data synchronization register
SCC1 event register
SCC1 mask register
SCC1 status register
Ñ
SCC2 general mode register (low)
SCC2 general mode register (high)
SCC2 protocol-speciÞc mode register
Ñ
SCC2 transmit-on-demand register
SCC2 data synchronization register
SCC2 event register
SCC2 mask register
SCC2 status register
Ñ
MPC8260 PowerQUICC II UserÕs Manual
Size
16 bits
2 bytes
16 bits
16 bits
16 bits
16 bits
8 bits
8 bytes
SCC2
32 bits
32 bits
16 bits
2 bytes
16 bits
16 bits
16 bits
16 bits
8 bits
8 bytes
Section/Page Number
19.1.2/19-9
20.16/20-13 (UART)
21.8/21-7 (HDLC)
22.11/22-10 (BISYNC)
23.9/23-9 (Transparent)
24.17/24-15 (Ethernet)
Ñ
19.1.4/19-9
19.1.3/19-9
20.19/20-19 (UART)
21.11/21-12 (HDLC)
22.14/22-15 (BISYNC)
23.12/23-12 (Transparent)
24.20/24-21 (Ethernet)
20.20/20-21 (UART)
21.12/21-14 (HDLC)
22.15/22-16 (BISYNC)
23.13/23-13 (Transparent)
Ñ
19.1.1/19-3
19.1.2/19-9
20.16/20-13 (UART)
21.8/21-7 (HDLC)
22.11/22-10 (BISYNC)
23.9/23-9 (Transparent)
24.17/24-15 (Ethernet)
Ñ
19.1.4/19-9
19.1.3/19-9
20.19/20-19 (UART)
21.11/21-12 (HDLC)
22.14/22-15 (BISYNC)
23.12/23-12 (Transparent)
24.20/24-21 (Ethernet)
20.20/20-21 (UART)
21.12/21-14 (HDLC)
22.15/22-16 (BISYNC)
23.13/23-13 (Transparent)
Ñ
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