Motorola MPC8260 PowerQUICC II User Manual page 328

Part III. The Hardware Interface
10.5.1 Timing ConÞguration
If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx.
These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds.
Table 10-30 shows signal behavior and system response.
Option Register Attributes
TRLX Access ACS CSNT
0 Read 00
0 Read 10
0 Read 11
0 Write 00
0 Write 10
0 Write 11
0 Write 00
0 Write 10
0 Write 11
1 Read 00
1 Read 10
1 Read 11
1 Write 00
1 Write 10
1 Write 11
1 Write 00
1 Write 10
1 Write 11
1
SCY is the number of wait cycles from the option register.
10-52
MPC8260
CSx
WE[0–3]
GPL_x1/OE
A[15–29]
D[0–31]
Figure 10-40. GPCM-to-SRAM ConÞguration
Table 10-30. GPCM Strobe Signal Behavior
Address to CS
Asserted
x 0
x 1/4*Clock
x 1/2*Clock
0 0
0 1/4*Clock
0 1/2*Clock
1 0
1 1/4*Clock
1 1/2*Clock
x 0
x (1+1/4)*Clock
x (1+1/2)*Clock
0 0
0 (1+1/4)*Clock
0 (1+1/2)*Clock
1 0
1 (1+1/4)*Clock
1 (1+1/2)*Clock
MPC8260 PowerQUICC II UserÕs Manual
32-Bit Wide SRAM
CE
WE[0–3]
OE
Address
Data
Signal Behavior
CS Negated to WE Negated to
Address Change Address/Data Invalid
0
0
0
0
0
0
0
-1/4*Clock
-1/4*Clock
0
0
0
0
0
0
0
-1-1/4*Clock
-1-1/4*Clock
128K
Total Cycles
x 2+SCY
x 2+SCY
x 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
-1/4*Clock 2+SCY
-1/4*Clock 2+SCY
-1/4*Clock 2+SCY
x 2+2*SCY
x 3+2*SCY
x 3+2*SCY
0 2+2*SCY
0 3+2*SCY
0 3+2*SCY
-1-1/4*Clock 3+2*SCY
-1-1/4*Clock 4+2*SCY
-1-1/4*Clock 4+2*SCY
MOTOROLA
1