Ethernet Mode Register (Psmr) - Motorola MPC8260 PowerQUICC II User Manual

Error
Heartbeat Some transceivers have a heartbeat (signal-quality error) self-test. To signify a good self-test,
the transceiver indicates a collision to the MPC8260 within 20 clocks after the Ethernet
controller sends a frame. This heartbeat condition does not imply a collision error, but that the
transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the MPC8260 does not
detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel
closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
Table 24-4 describes reception errors.
Error
Overrun The Ethernet controller maintains an internal FIFO for receiving data. When it overruns, the channel
writes the received byte over the previously received byte. The previous byte and frame status are lost.
The channel closes the buffer, sets RxBD[OV] and SCCE[RXF], and increments the discarded frame
counter (DISFC). The receiver then enters hunt mode.
Busy A frame was received and discarded because of a lack of buffers. The channel sets SCCE[BSY] and
increments DISFC. The receiver then enters hunt mode.
Non-Octet The Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet
Error aligned. It checks the CRC of the frame on the last octet boundary. If there is a CRC error, a frame
(Dribbling nonoctet aligned error is reported, SCCE[RXF] is set, and the alignment error counter is incremented. If
Bits) there is no CRC error, no error is reported. The receiver then enters hunt mode.
CRC When a CRC error occurs, the channel closes the buffer, sets SCCE[RXF] and CR in the RxBD, and
increments the CRC error counter (CRCEC). After receiving a frame with a CRC error, the receiver enters
hunt mode. CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required.

24.17 Ethernet Mode Register (PSMR)

In Ethernet mode, the protocol-speciÞc mode register (PSMR), shown in Figure 24-5, is
used as the Ethernet mode register.
Bit 0 1 2
Field HBC FC RSH IAM
Reset
R/W
Addr 0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)
MOTOROLA
Table 24-4. Transmission Errors (Continued)
Table 24-5. Reception Errors
3 4 5 6
CRC PRO BRO SBT
0000_0000_0000_0000
Figure 24-5. Ethernet Mode Register (PSMR)
Chapter 24. SCC Ethernet Mode
Part IV. Communications Processor Module
Description
Description
7 8 9 10
LPB Ñ LCW
R/W
11 12 13 14
NIB FDE
24-15
15