Motorola MPC8260 PowerQUICC II User Manual page 92

Part I. Overview
¥ Four independent execution units and two register Þles
Ñ BPU featuring static branch prediction
Ñ A 32-bit IU
Ñ LSU for data transfer between data cache and GPRs and FPRs
Ñ SRU that executes condition register (CR), special-purpose register (SPR), and
integer add/compare instructions
Ñ Thirty-two GPRs for integer operands
Ñ Thirty-two FPRs. These can be used for operands for ßoating-point load and
store operands,
¥ High instruction and data throughput
Ñ Zero-cycle branch capability (branch folding)
Ñ Programmable static branch prediction on unresolved conditional branches
Ñ BPU that performs CR lookahead operations
Ñ Instruction fetch unit capable of fetching two instructions per clock from the
instruction cache
Ñ A six-entry instruction queue that provides lookahead capability
Ñ Independent pipelines with feed-forwarding that reduces data dependencies in
hardware
Ñ 16-Kbyte data cacheÑfour-way set-associative, physically addressed; LRU
replacement algorithm
Ñ 16-Kbyte instruction cacheÑfour-way set-associative, physically addressed;
LRU replacement algorithm
Ñ Cache write-back or write-through operation programmable on a per page or per
block basis
Ñ Address translation facilities for 4-Kbyte page size, variable block size, and
256-Mbyte segment size
Ñ A 64-entry, two-way set-associative ITLB
Ñ A 64-entry, two-way set-associative DTLB
Ñ Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte
blocks
Ñ Software table search operations and updates supported through fast trap
mechanism
Ñ 52-bit virtual address; 32-bit physical address
¥ Facilities for enhanced system performance
Ñ A 32- or 64-bit, split-transaction external data bus with burst transfers
Ñ Support for one-level address pipelining and out-of-order bus transactions
Ñ Hardware support for misaligned little-endian accesses
Ñ Added bus multipliers of 4.5x, 5x, 5.5x, 6x, 6.5x 7x, 7.5x, 8x. See Figure 2-3.
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