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Figure
Number
10-41
GPCM Peripheral Device Interface ....................................................................... 10-53
10-42
GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................... 10-53
10-43
GPCM Memory Device Interface.......................................................................... 10-54
10-44
GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) ......... 10-54
GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0) ......... 10-55
10-45
10-46
GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) ....... 10-55
10-47
GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)....... 10-56
10-48
GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)...... 10-56
10-49
GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)...... 10-57
10-50
GPCM Read Followed by Read (ORx[29Ð30] = 0x, Fastest Timing) .................. 10-58
10-51
GPCM Read Followed by Read (ORx[29Ð30] = 01) ............................................ 10-59
10-52
GPCM Read Followed by Write (ORx[29Ð30] = 01) ........................................... 10-59
10-53
GPCM Read Followed by Read (ORx[29Ð30] = 10) ............................................ 10-60
10-54
External Termination of GPCM Access ................................................................ 10-61
10-55
User-Programmable Machine Block Diagram ...................................................... 10-63
10-56
RAM Array Indexing............................................................................................. 10-64
10-57
Memory Refresh Timer Request Block Diagram .................................................. 10-66
10-58
Memory Controller UPM Clock Scheme for Integer Clock Ratios ...................... 10-67
10-59
Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)
Clock Ratios ........................................................................................................ 10-68
10-60
UPM Signals Timing Example.............................................................................. 10-69
10-61
RAM Array and Signal Generation ....................................................................... 10-70
10-62
The RAM Word..................................................................................................... 10-70
10-63
CS Signal Selection ............................................................................................... 10-75
10-64
BS Signal Selection ............................................................................................... 10-75
10-65
UPM Read Access Data Sampling ........................................................................ 10-78
10-66
Wait Mechanism Timing for Internal and External Synchronous Masters ........... 10-79
10-67
DRAM Interface Connection to the 60x Bus (64-Bit Port Size) ........................... 10-82
10-68
Single-Beat Read Access to FPM DRAM............................................................. 10-83
10-69
Single-Beat Write Access to FPM DRAM ............................................................ 10-84
10-70
Burst Read Access to FPM DRAM (No LOOP) ................................................... 10-85
10-71
Burst Read Access to FPM DRAM (LOOP) ......................................................... 10-86
10-72
Burst Write Access to FPM DRAM (No LOOP) .................................................. 10-87
10-73
Refresh Cycle (CBR) to FPM DRAM................................................................... 10-88
10-74
Exception Cycle..................................................................................................... 10-89
10-75
FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) ... 10-91
10-76
MPC8260/EDO Interface Connection to the 60x Bus........................................... 10-92
10-77
Single-Beat Read Access to EDO DRAM............................................................. 10-93
10-78
Single-Beat Write Access to EDO DRAM............................................................ 10-94
10-79
Single-Beat Write Access to EDO DRAM Using REDO to Insert Three
Wait States........................................................................................................... 10-95
10-80
Burst Read Access to EDO DRAM....................................................................... 10-96
10-81
Burst Write Access to EDO DRAM ...................................................................... 10-97
xxxvi
ILLUSTRATIONS
Title
MPC8260 PowerQUICC II UserÕs Manual
Page
Number
MOTOROLA
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