Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm) - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
The data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).Ó
21.11 HDLC Event Register (SCCE)/HDLC Mask
Register (SCCM)
The SCC event register (SCCE) is used as the HDLC event register to report events
recognized by the HDLC channel and to generate interrupts. When an event is recognized,
the SCC sets the corresponding SCCE bit. Interrupts generated through SCCE can be
masked in the SCC mask register (SCCM) which has the same bit format as the SCCE.
Setting an SCCM bit enables the corresponding interrupt; clearing a bit masks it. SCCE bits
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared
before the CP clears the internal interrupt request. Figure 21-7 shows SCCE/SCCM for
HDLC operation.
Bit 0 1 2
Field Ñ
Reset
R/W
Addr 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)
Figure 21-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
Table 21-9 describes SCCE/SCCM Þelds.
Bits Name
0Ð2 Ñ Reserved, should be cleared.
3, 4 GLR/ Glitch on Rx/Tx. Set when the SCC detects a clock glitch on the receive/transmit clock. See
GLT Section 19.3.7, ÒClock Glitch Detection.Ó
5 DCC DPLL carrier sense changed. Set when the carrier sense status generated by the DPLL changes.
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only
when the DPLL is used.
6 FLG Flag status. Set when the SCC stops or starts receiving HDLC ßags. Real-time status can be read in
SCCS[FG].
7 IDL Idle sequence status changed. Set when HDLC line status changes. Real-time status of the line can
be read in SCCS[ID].
8 GRA Graceful stop complete. A
the transmitter has sent a frame in progress when the command was issued. Set immediately if no
frame was in progress when the command was issued.
9Ð10 Ñ Reserved, should be cleared.
11 TXE Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel.
21-12
3 4 5 6
GLR GLT DCC FLG
0000_0000_0000_0000
Table 21-9. SCCE/SCCM Field Descriptions
GRACEFUL STOP TRANSMIT
MPC8260 PowerQUICC II UserÕs Manual
7 8 9 10
IDL GRA Ñ
R/W
Description
command completed execution. Set as soon as
11 12 13 14
TXE RXF BSY TXB RXB
MOTOROLA
15