Table of Contents
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H
HDLC mode
accessing the bus, 21-19
bus controller, 21-17
collision detection, 21-17, 21-20
commands, 21-5
delayed RTS mode, 21-21
error handling, 21-6
fast communications controllers (FCCs)
bit stuffing, 31-1
error control, 31-1
error handling, 31-6
FCCE, 31-14
FCCM, 31-14
FCCS, 31-16
features list, 31-2
FPSMR, 31-7
frame reception, 31-3
frame transmission, 31-2
overview, 31-1
parameter RAM, 31-4
programming model, 31-5
receive commands, 31-6
reception errors, 31-7
RxBD, 31-9
transmission errors, 31-6
transmit commands, 31-5
TxBD, 31-12
features list, 21-2
GSMR, HDLC bus protocol programming, 21-23
multi-master bus configuration, 21-18
overview, 21-1
parameter RAM, 21-3
performance, increasing, 21-20
programming example, 21-15, 21-23
programming the controller, 21-5
PSMR, 21-7
RxBD, 21-8
single-master bus configuration, 21-19
TxBD, 21-11
using the TSA, 21-22
HID0 register
bit settings, 2-12
doze, nap, sleep, DPM bits, 2-12
I
2
I2ADD (I
C address) register, 34-7
2
I2BRG (I
C baud rate generator) register, 34-7
2
I
C controller
block diagram, 34-1
BRGCLK, 34-2
clocking and pin functions, 34-2
commands, 34-11
Index-10
INDEX
MPC8260 PowerQUICC II UserÕs Manual
features list, 34-2
loopback testing, 34-4
master read (slave write), 34-4
master write (slave read), 34-4
multi-master considerations, 34-5
parameter RAM, 34-9
programming model, 34-6
registers, 34-6
RxBD, 34-13
slave read (master write), 34-4
slave write (master read), 34-4
transfers, 34-3
TxBD, 34-14
2
I
C memory map, 3-9
2
I2CER (I
C event register), 34-8
2
I2CMR (I
C mask register), 34-8
2
I2COM (I
C command) register, 34-8
2
I2MOD (I
C mode) register, 34-6
IDL interface programming, 14-29
IDL interface support, 14-25
IDMA emulation
auto buffer, 18-15
buffer chaining, 18-15
buffers, 18-23
bus exceptions, 18-27
commands, 18-26
controlling 60x bus bandwidth, 18-12
DACKx, 18-13
DCM, 18-18
DONEx, 18-14
DREQx, 18-13
DTS/STS programming, 18-20
dual-address transfers, 18-10
edge-sensitive mode, 18-13
exception, bus, 18-27
external request mode, 18-8
features list, 18-5
IDMR, 18-22
IDSR, 18-22
level-sensitive mode, 18-13
normal mode, 18-9
operand transfers, recognizing, 18-27
operation, 18-14
overview, 18-5
parallel I/O register programming, 18-28
parameter RAM, 18-16
priorities, 18-12
programming examples, 18-29
programming the parallel I/O registers, 18-28
signals, 18-12
single address transfers (fly-by), 18-11
transfers, 18-6
IDMA parameter RAM, 18-16
IDMR (IDMA mask registers), 18-22
MOTOROLA
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