Motorola MPC8260 PowerQUICC II User Manual page 24

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27.1 Features...............................................................................................................27-1
27.2 MCC Data Structure Organization .....................................................................27-2
27.3 Global MCC Parameters.....................................................................................27-3
27.4 Channel Extra Parameters ..................................................................................27-5
27.5 Super-Channel Table ..........................................................................................27-5
27.6 Channel-Specific HDLC Parameters..................................................................27-8
27.6.1 Internal Transmitter State (TSTATE) ............................................................27-9
27.6.2 Interrupt Mask (INTMSK) .............................................................................27-9
27.6.3 Channel Mode Register (CHAMR)..............................................................27-10
27.6.4 Internal Receiver State (RSTATE)...............................................................27-11
27.7 Channel-Specific Transparent Parameters........................................................27-12
27.7.1 Channel Mode Register (CHAMR)ÑTransparent Mode ............................27-13
27.8 MCC Configuration Registers (MCCFx) .........................................................27-15
27.9 MCC Commands ..............................................................................................27-16
27.10 MCC Exceptions...............................................................................................27-17
27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM) .............................27-18
27.10.1.1 Interrupt Table Entry ................................................................................27-19
27.11 MCC Buffer Descriptors ..................................................................................27-21
27.11.1 Receive Buffer Descriptor (RxBD) ..............................................................27-21
27.11.2 Transmit Buffer Descriptor (TxBD).............................................................27-23
27.12 MCC Initialization and Start/Stop Sequence....................................................27-24
27.12.1 Single-Channel Initialization........................................................................27-25
27.12.2 Super Channel Initialization .........................................................................27-26
27.13 MCC Latency and Performance .......................................................................27-26
28.1 Overview ............................................................................................................28-2
28.2 General FCC Mode Registers (GFMRx)............................................................28-3
28.3 FCC Protocol-Specific Mode Registers (FPSMRx)...........................................28-7
28.4 FCC Data Synchronization Registers (FDSRx) .................................................28-7
28.5 FCC Transmit-on-Demand Registers (FTODRx) ..............................................28-7
28.6 FCC Buffer Descriptors......................................................................................28-8
28.7 FCC Parameter RAM .......................................................................................28-10
28.7.1 FCC Function Code Registers (FCRx).........................................................28-13
28.8 Interrupts from the FCCs..................................................................................28-13
28.8.1 FCC Event Registers (FCCEx).....................................................................28-14
28.8.2 FCC Mask Registers (FCCMx) ....................................................................28-14
xxiv
CONTENTS
Chapter 27
Multi-Channel Controllers (MCCs)
Chapter 28
Fast Communications Controllers (FCCs)
MPC8260 PowerQUICC II UserÕs Manual
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MOTOROLA