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Part IV. Communications Processor Module
17.2.5 Timer Capture Registers (TCR1ÐTCR4)
Each timer capture register (TCR1ÐTCR4), shown in Figure 17-7, is used to latch the value
of the counter according to TMRx[CE].
Bit
0
1
2
Field
Reset
R/W
Addr
Figure 17-7. Timer Capture Registers (TCR1ÐTCR4)
17.2.6 Timer Counters (TCN1ÐTCN4)
Each timer counter register (TCN1ÐTCN4), shown in Figure 17-8, is an up-counter. A read
cycle to TCNx yields the current value of the timer but does not affect the counting
operation. A write cycle to TCNx sets the register to the written value, thus causing its
corresponding prescaler, TMRx[PS], to be reset.
Bit
0
1
2
Field
Reset
R/W
Addr
0x10D9C (TCN1), 0x10D9E (TCN2), 0x10DAC (TCN3), 0x10DAE (TCN4)
Figure 17-8. Timer Counter Registers (TCN1ÐTCN4)
Note that the counter registers may not be updated correctly if a write is made while the
timer is not running. Use TRRx to deÞne the preferred count value.
17.2.7 Timer Event Registers (TER1ÐTER4)
Each timer event register (TERx), shown in Figure 17-9, reports events recognized by the
timers. When an output reference event is recognized, the timer sets TERx[REF] regardless
of the corresponding TMRx[ORI]. The capture event is set only if it is enabled by
TMRx[CE]. TER1ÐTER4 can be read at any time.
Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared
before the timer negates the interrupt.
Bits
0
1
2
Field
Reset
Addr
Figure 17-9. Timer Event Registers (TER1ÐTER4)
17-8
3
4
5
6
Latched counter value
0x10D98 (TCR1), 0x10D9A (TCR2), 0x10DA8 (TCR3), 0x10DAA (TCR4)
3
4
5
6
3
4
5
6
0x10DB0 (TER1); 0x10DB2 (TER2); 0x10DB4 (TER3); 0x10DB6 (TER4)
MPC8260 PowerQUICC II UserÕs Manual
7
8
9
10
0x0000
R/W
7
8
9
10
Up counter
0x0000
R/W
7
8
9
10
Ñ
0x0000
11
12
13
14
11
12
13
14
11
12
13
14
REF CAP
MOTOROLA
15
15
15
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