Address Multiplexing; Data Valid And Data Sample Control - Motorola MPC8260 PowerQUICC II User Manual

Figure 10-79 shows an example of REDO use.

10.6.4.2 Address Multiplexing

The address lines can be controlled by the pattern the user provides in the UPM. The
address multiplex bits can choose between outputting an address requested by the internal
master as is and outputting it according to the multiplexing speciÞed by the MxMR[AMx].
The last option is to output the contents of the MAR on the address pins.
Note that in 60x-compatible mode, MAR cannot be output on the 60x bus external address
line.
Note that on the local bus, only the lower 18 bits of the MAR are output.
Table 10-37 shows how MxMR[AMx] settings affect address multiplexing.
External Bus
AMx A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Address Pin
000 A8
001 A7
Signal Driven
on External
010 A6
Pin when
Address
011 A5
Multiplexing
is Enabled
100 Ñ
101 Ñ
See Section 10.6.5, ÒUPM DRAM ConÞguration Example,Ó for more details.

10.6.4.3 Data Valid and Data Sample Control

When a read access is handled by the UPM and the UTA bit is 1, the value of the DLT3 bit
in the same RAM word indicates when the data input is sampled by the internal bus master,
assuming that MxMR[GPLx4DIS] = 1.
¥ If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched
on the falling edge of CLKIN instead of the rising edge. The data is sampled by the
internal master on the next rising edge as is required by the MPC8260 bus operation
spec. This feature lets the user speed up the memory interface by latching data 1/2
clock early, which can be useful during burst reads. This feature should be used only
in systems without external synchronous bus devices.
¥ If G4T4/DLT3 functions as G4T4, data is latched on the rising edge of CLKIN, as
is normal in MPC8260 bus operation.
Figure 10-65 shows data sampling that is controlled by the UPM.
MOTOROLA
Table 10-37. UPM Address Multiplexing
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
A5 A6 A7 A8 A9
Ñ A5 A6 A7 A8
Chapter 10. Memory Controller
Part III. The Hardware Interface
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
10-77