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Chapter 5
Reset
50
50
The MPC8260 has several inputs to the reset logic:
¥ Power-on reset (PORESET)
¥ External hard reset (HRESET)
¥ External soft reset (SRESET)
¥ Software watchdog reset
¥ Bus monitor reset
¥ Checkstop reset
¥ JTAG reset
All of these reset sources are fed into the reset controller and, depending on the source of
the reset, different actions are taken. The reset status register, described in Section 5.2,
ÒReset Status Register (RSR),Ó indicates the last sources to cause a reset.
5.1 Reset Causes
Table 5-1 describes reset causes.
Name
Power-on reset
Input pin. Asserting this pin initiates the power-on reset ßow that resets all the chip and conÞgures
(PORESET)
various attributes of the chip including its clock mode.
Hard reset
This is a bidirectional I/O pin. The MPC8260 can detect an external assertion of HRESET only if it
(HRESET)
occurs while the MPC8260 is not asserting reset. During HRESET, SRESET is asserted. HRESET is
an open-collector pin.
Soft reset
Bidirectional I/O pin. The MPC8260 can only detect an external assertion of SRESET if it occurs while
(SRESET)
the MPC8260 is not asserting reset. SRESET is an open-drain pin.
Software
After the MPC8260Õs watchdog counts to zero, a software watchdog reset is signaled. The enabled
watchdog reset
software watchdog event then generates an internal hard reset sequence.
Bus monitor
After the MPC8260s bus monitor counts to zero, a bus monitor reset is asserted. The enabled bus
reset
monitor event then generates an internal hard reset sequence.
Checkstop
If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), the checkstop
reset
reset is asserted. The enabled checkstop event then generates an internal hard reset sequence.
JTAG reset
When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated.
MOTOROLA
Table 5-1. Reset Causes
Description
Chapter 5. Reset
5-1
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