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The 60x bus is pipelined. The ALE pins control the external latch that latches the address
from the 60x bus and keeps the address stable for the memory access. The memory
controller asserts ALE only on the start of new memory controller access.
Figure 10-84 shows the pipelined bus operation in 60x-compatible mode.
CLKIN
ADDR + ATTR
TS
AACK
DBG
PSDVAL
TA
D
ALE
MA
CS
WE
OE
BADDR[27–28]
Figure 10-84. Pipelined Bus Operation and Memory Access in 60x-Compatible
MOTOROLA
00
Mode
Chapter 10. Memory Controller
Part III. The Hardware Interface
02
03
01
10-103
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