Motorola MPC8260 PowerQUICC II User Manual page 952

Part IV. Communications Processor Module
Table 34-6. I
1
Offset Name Width
0x06 MRBLR Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260
0x08 RSTATE Word
0x0C RPTR Word
0x10 RBPTR Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in an
0x12 RCOUNT Hword Rx internal byte count
0x14 RTEMP Word
0x18 TSTATE Word
0x1C TPTR Word
0x20 TBPTR Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from when
0x22 TCOUNT Hword Tx internal byte count
0x24 TTEMP Word
1
From the pointer value programmed in I2C_BASE at IMMR + 0x8AFC.
2
Normally, these parameters need not be accessed.
34-10
2
C Parameter RAM Memory Map (Continued)
writes to a Rx buffer before moving to the next buffer. The MPC8260 writes fewer bytes
to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should not
be smaller than MRBLR.
Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be
sent is speciÞed in TxBD[Data Length].
MRBLR is not intended to be changed while the I
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-
back). The change takes effect when the CP moves control to the next RxBD. To
guarantee the exact RxBD on which the change occurs, change MRBLR only while the
2
I C receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
Rx internal state. Reserved for CP use.
2
Rx internal data pointer is updated by the SDMA channels to show the next address in
the buffer to be accessed.
idle state or to the current descriptor during frame processing for each I
a reset or when the end of the descriptor table is reached, the CP initializes RBPTR to
the value in RBASE. Most applications should not write RBPTR, but it can be modiÞed
when the receiver is disabled or when no receive buffer is used.
2
is a down-count value that is initialized with the MRBLR value
and decremented with every byte the SDMA channels write.
2
Rx temp. Reserved for CP use.
2
Tx internal state. Reserved for CP use.
2
Tx internal data pointer is updated by the SDMA channels to show the next address in
the buffer to be accessed.
it is in an idle state or to the current descriptor during frame transmission. After a reset or
when the end of the descriptor table is reached, the CP initializes TBPTR to the value in
TBASE.Most applications should not write TBPTR, but it can be modiÞed when the
transmitter is disabled or when no transmit buffer is used.
2
is a down-count value initialized with TxBD[Data Length] and
decremented with every byte read by the SDMA channels.
2
Tx temp. Reserved for CP use.
MPC8260 PowerQUICC II UserÕs Manual
Description
2
C is operating. However it can be
2
C channel. After
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