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Signal
BADDR[27Ð28] Burst address 27:28ÑThere are Þve burst address output pins. These pins are outputs of the 60x
memory controller. Used in external master conÞguration and connected directly to the memory
devices controlled by MPC8260Õs memory controller.
ALE
Address latch enableÑThis output pin controls the external address latch that should be used in
external master 60x bus conÞguration.
BCTL0
Buffer control 0ÑOutput whose function is controlling buffers on the 60x data bus. Usually used
with BCTL1 that is multiplexed on CS10. The exact function of this pin is deÞned by the value of
SIUMCR[BCTLC]. See Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR),Ó for details.
PWE[0Ð7]
60x bus write enableÑOutputs of the 60x bus GPCM. These pins select byte lanes for write
PSDDQM[0Ð7]
operations.
PBS[0Ð7]
60x bus SDRAM DQMÑThe DQM pins are outputs of the SDRAM control machine. These pins
select speciÞc byte lanes of SDRAM devices.
60x bus UPM byte selectÑThe byte select pins are outputs of the UPM in the memory controller.
They are used to select speciÞc byte lanes during memory operations. The timing of these pins is
programmed in the UPM. The actual driven value depends on the address and size of the
transaction and the port size of the accessed device.
PSDA10
60x bus SDRAM A10Ñ(Output) from the 60x bus SDRAM controller. Part of the address when a
PGPL0
row address is driven and is part of the command when a column address is driven.
60x bus UPM general purpose line 0ÑThis is one of six general purpose output lines from UPM.
The values and timing of this pin is programmed in the UPM.
PSDWE
60x bus SDRAM write enableÑ(Output) from the 60x bus SDRAM controller. Should be connected
PGPL1
to SDRAMsÕ WE input.
60x bus UPM general purpose line 1ÑThis is one of six general purpose output lines from UPM.
The values and timing of this pin is programmed in the UPM.
POE
60x bus output enableÑThe output enable pin is an output of the 60x bus GPCM. Controls the
PSDRAS
output buffer of memory devices during read operations.
PGPL2
60x bus SDRAM rasÑOutput from the 60x bus SDRAM controller. Should be connected to
SDRAMsÕ RAS input.
60x bus UPM general purpose line 2ÑThis is one of six general purpose output lines from UPM.
The values and timing of this pin is programmed in the UPM.
PSDCAS
60x bus SDRAM CASÑOutput from the 60x bus SDRAM controller. Should be connected to
PGPL3
SDRAMsÕ CAS input.
60x bus UPM general purpose line 3ÑThis is one of six general purpose output lines from UPM.
The values and timing of this pin is programmed in the UPM.
PGTA
60x GPCM TAÑThis input pin is used for transaction termination during GPCM operation. Requires
PUPMWAIT
external pull up resistor for proper operation.
PGPL4
60x bus UPM waitÑThis is an input to the UPM. An external device may hold this pin low to force
PPBS
the UPM to wait until the device is ready for the continuation of the operation.
60x bus UPM general purpose line 4ÑThis is one of six general purpose output lines from UPM.
The values and timing of this pin is programmed in the UPM.
60x bus parity byte selectÑIn systems in which data parity is stored in a separate chip, this output
is used as the byte-select for that chip.
PSDAMUX
60x bus SDRAM address multiplexerÑThis output pin controls the 60x SDRAM address multiplexer
PGPL5
when the MPC8260 is in external master mode.
60x bus UPM general purpose line 5ÑThis is one of six general purpose output lines from UPM.
The values and timing of this pin is programmed in the UPM.
MOTOROLA
Table 6-1. External Signals (Continued)
Chapter 6. External Signals
Part III. The Hardware Interface
Description
6-7
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