Atm Controller Buffers; Aal5 Rxbd - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
Table 29-33. Free Buffer Pool Parameter Table (Continued)
1
Offset Bits Name
8 EPD
9Ð15 Ñ
0x0C Ñ FBP_ENTRY
1 Offset from FBT_BASE+RCT[BPOOL] ´ 16

29.10.5.3 ATM Controller Buffers

Table 29-34 describes properties of the ATM receive and transmit buffers.
AAL
AAL5 Multiple of 48 octets (except last buffer in frame)
AAL1 At least 47 octets
AAL0 52-64 octets.

29.10.5.4 AAL5 RxBD

Figure 29-46 shows the AAL5 RxBD.
0 1
Offset + 0x00 E Ñ
Offset + 0x02
Offset + 0x04
Offset + 0x06
29-69
Early packet discard.
0 Normal operation.
1 AAL5 frames in progress are received, but new AAL5 frames associated with
this pool are discarded. Can be used to implement EPD under core control.
Reserved, should be cleared.
Free buffer pool entry. Initialize with the Þrst entry of the free buffer pool. Note
that FBP_ENTRY must be reinitialized when a busy state occurs.
Table 29-34. Receive and Transmit Buffers
Receive
Size
2 3 4 5 6
W I L F CM
Rx Data Buffer Pointer (RXDBPTR)
Figure 29-46. AAL5 RxBD
MPC8260 PowerQUICC II UserÕs Manual
Description
Alignment
Double word aligned Any
No requirement At least 47 octets No requirement
Burst-aligned 52Ð64 octets.
7 8 9 10 11
Ñ CLP CNG ABRT CPUU LNE CRE
Data Length (DL)
Transmit
Size Alignment
No requirement
No requirement
12 13 14 15
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