Motorola MPC8260 PowerQUICC II User Manual page 470

Part IV. Communications Processor Module
Initial State
1)
The TSA uses the first part of
the RAM, and the shadow is
the second part of the RAM.
CSRxn = 0
CSRRa=0
CSRTa=0
CSRRb=0
CSRTb=0
Programming
2)
The user programs the
shadow RAM for the new
Rx and Tx route and sets
CSRxn.
CSRRa=1
CSRTa=1
CSRRb=1
CSRTb=1
Swap
3)
The SI swaps between
the shadow and the
current-route RAMs
and resets CSRxn.
CSRRa=0
CSRTa=0
CSRRb=0
CSRTb=0
Figure 14-9. Example: SI x RAM Dynamic Changes, TDMa and b, Same SI x RAM Size
14-16
RAM Address: 0
64 TXa
Route
L1TCLKa
Framing Signals:
L1TSYNCa
RAM Address: 1024
64 RXa
Route
L1RCLKa
Framing Signals:
L1RSYNCa
0
RAM Address:
64 TXa
Route
L1TCLKa
Framing Signals: L1TSYNCa
1024
RAM Address:
64 RXa
Route
L1RCLKa
Framing Signals: L1RSYNCa
RAM Address: 0
64 TXa
Shadow
Framing Signals:
1024
RAM Address:
64 RXa
Shadow
Framing Signals:
MPC8260 PowerQUICC II UserÕs Manual
127 128 255 256
64 TXb
64 TXa
Shadow Route
L1TCLKb
L1TSYNCb
1151 1152 1279 1280
64 RXb
64 RXa
Shadow Route
L1RCLKb
L1RSYNCb
127 128 255 256
64 TXb
64 TXa
Shadow Route
L1TCLKb
L1TSYNCb
1151 1152 1279 1280
64 RXb
64 RXa
Shadow
Route
L1RCLKb
L1RSYNCb
127 128 255 256
64 TXb
64 TXa
Route Shadow
L1TCLKa
L1TSYNCa
1151 1152 1279 1280
64 RXb
64 RXa
Route Shadow
L1RCLKa
L1RSYNCa
383 384 511
64 TXb
Shadow
1407 1408 1535
64 RXb
Shadow
383 384 511
64 TXb
Shadow
1407 1408 1535
64 RXb
Shadow
383 384 511
64 TXb
Route
L1TCLKb
L1TSYNCb
1407 1408 1535
64 RXb
Route
L1RCLKb
L1RSYNCb
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