Motorola MPC8260 PowerQUICC II User Manual page 98

Part I. Overview
USER MODEL
UISA
General-Purpose
Registers
GPR0
GPR1
GPR31
Floating-Point
2
Registers
FPR0
FPR1
FPR31
Condition Register
CR
XER
XER
SPR 1
Link Register
LR
SPR 8
Count Register
CTR
SPR 9
USER MODEL
VEA
Time Base Facility
(For Reading)
TBL TBR 268
TBU TBR 269
.
1
These implementationÐspecific registers may not be supported by other PowerPC processors or processor cores.
2
Although the MPC8260 does not implement an FPU, the LSU can access FPRs if MSR[FP] = 1.
Figure 2-2. MPC8260 Programming ModelÑRegisters
2-10
SUPERVISOR MODELÑOEA
Configuration Registers
Hardware
Implementation
1
Registers
HID0 SPR 1008
HID1 SPR 1009
HID2 SPR 1011
Memory Management Registers
Instruction BAT
Data BAT Registers
Registers
IBAT0U SPR 528
IBAT0L SPR 529
IBAT1U SPR 530
IBAT1L SPR 531
IBAT2U SPR 532
IBAT2L SPR 533
IBAT3U SPR 534
IBAT3L SPR 535
SDR1
SDR1 SPR 25
Exception Handling Registers
Data Address Register
DAR
SPR 19
SPRGs
SPRG0 SPR 272
SPRG1 SPR 273
SPRG2 SPR 274
SPRG3 SPR 275
Miscellaneous Registers
Time Base Facility
(For Writing)
TBL SPR 284
TBU SPR 285
Instruction Address
Breakpoint Register
IABR SPR 1010
MPC8260 PowerQUICC II UserÕs Manual
Machine State
Register
MSR
DBAT0U SPR 536
DBAT0L SPR 537
DBAT1U SPR 538
DBAT1L SPR 539
DBAT2U SPR 540
DBAT2L SPR 541
DBAT3U SPR 542
DBAT3L SPR 543
Segment Registers
DSISR
DSISR
Save and Restore Registers
SRR0
SRR1
Decrementer
DEC
External Address
1
Register (Optional)
EAR
Processor Version
Register
PVR SPR 287
Software Table
1
Search Registers
DMISS SPR 976
DCMP SPR 977
HASH1 SPR 978
HASH2 SPR 979
IMISS SPR 980
ICMP SPR 981
RPA SPR 982
SR0
SR1
SR15
SPR 18
SPR 26
SPR 27
SPR 22
SPR 282
MOTOROLA