Motorola MPC8260 PowerQUICC II User Manual page 968

Part IV. Communications Processor Module
Table 35-6 shows the port B pin assignments.
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1)
Pin
PDIRB = 1 (Output)
PB31 FCC2: TX_ER
MII
PB30 FCC2: TxSOC
UTOPIA
PB29 FCC2: RxClav
UTOPIA slave
PB28 FCC2: RTS
PB27 FCC2: TxD[0]
UTOPIA 8
PB26 FCC2: TxD[1]
UTOPIA 8
PB25 FCC2: TxD[4]
UTOPIA 8
FCC2: TxD[3]
MII/HDLC/transp.
nibble
PB24 FCC2: TxD[5]
UTOPIA 8
FCC2: TxD[2]
MII/HDLC/transp.
nibble
PB23 FCC2: TxD[6]
UTOPIA
FCC2: TxD[1]
MII/HDLC/transp.
nibble
PB22 FCC2: TxD[7]
UTOPIA
FCC2: TxD[0]
MII/HDLC/transp.
nibble
FCC2: TxD
HDLC/transp. serial
PB21
35-12
Pin Function
PSORB = 0
Default
PDIRB = 0 (Input)
FCC2: RxSOC
UTOPIA
FCC2: RX_DV
MII
FCC2: RxClav
UTOPIA master
FCC2: RX_ER
MII
FCC2: COL
MII
FCC2: CRS
MII
TDM_A1: L1RXD[3]
Nibble
TDM_A1: L1RXD[2]
Nibble
TDM_A1: L1RXD[1]
Nibble
FCC2: RxD[7]
UTOPIA 8
FCC2: RxD[0]
MII/HDLC/transp. nibble
FCC2: RxD
HDLC/transp.. serial
MPC8260 PowerQUICC II UserÕs Manual
PDIRB = 1 (Output)
Input
GND
GND
GND FCC2: TX_EN
MII
GND SCC1: TXD
GND
GND
TDM_A1: L1TXD[3]
Nibble
GND
GND
GND
GND TDM_A1: L1TXD[2]
Nibble
PSORB = 1
PDIRB = 0 (Input or Default
Inout if SpeciÞed) Input
TDM_B2: L1TXD GND
Inout
TDM_B2: L1RXD GND
Inout
TDM_B2: L1RSYNC GND
TDM_B2: GND
L1TSYNC/GRANT
TDM_C2: L1TXD GND
Inout
TDM_C2: L1RXD GND
Inout
TDM_C2: GND
L1TSYNC/GRANT
TDM_C2: L1RSYNC GND
TDM_D2: L1TXD GND
Inout
TDM_D2: L1RXD GND
Inout
TDM_D2: GND
L1TSYNC/GRANT
MOTOROLA